DESCRIPTION
The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the ELT23 makes it ideal for applications that require the translation of a clock and a data signal.
The ELT23 is available in only the ECL 100K standard. Since there are no PECL outputs or an external VBB reference, the ELT23 does not require both ECL standard versions. The PECL inputs are differential; there is no specified difference between the differential input 10K and 100K standards. Therefore the AZ100ELT23 can accept any standard differential PECL input referenced from a VCC of 3.0V to 5.5V.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*Green / RoHS Compliant / Lead (Pb) Free package available
*3.5ns Typical Propagation Delay
*<500ps Typical Output to Output Skew
*Differential PECL Inputs
*CMOS/TTL Outputs
*Flow Through Pinouts
*Direct Replacement for ON Semiconductor MC100ELT23
*Operating Range of 3.0V to 5.5V (For operation down to 2.5V consult AZM)
*Use AZ100ELT23 for 10K Applications

AZ100ELT23D, AZ100ELT23D+, AZ100ELT23DG, AZ100ELT23T, AZ100ELT23T+
TAG CMOS, TTL

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General Description
The RT9187 is a high-performance, 1A LDO regulator, offering extremely high PSRR and ultra-low dropout. Ideal for portable RF and wireless applications with demanding performance and space requirements.
A noise reduction pin is also available for further reduction of output noise. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The RT9187 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices.
The RT9187 consumes less than 0.1uA in shutdown mode and has fast turn-on time less than 40μs. The other features include ultra-low dropout voltage, high output accuracy, current limiting protection, and high ripple rejection ratio. Available in the VDFN-8L 3x3 and SOP-8 (Exposed Pad) package.

Features
*Ultra-Low-Noise for RF Application
*Ultra-Fast Response in Line/Load Transient
*Quick Start-Up (Typically 40μs)
*< 0.1uA Standby Current When Shutdown
*Low Dropout : 240mV at 1A
*Wide Operating Voltage Ranges : 2.5V to 5.5V
*TTL-Logic-Controlled Shutdown Input
*Current Limiting Protection
*Thermal Shutdown Protection
*Only 2.2uF Output Capacitor Required for Stability
*High Power Supply Rejection Ratio
*RoHS Compliant and 100% Lead (Pb)-Free

Applications
*CDMA/GSM Cellular Handsets
*Battery-Powered Equipment
*Laptop, Palmtops, Notebook Computers
*Hand-Held Instruments
*Mini PCI & PCI-Express Cards
*PCMCIA & New Cards
*Portable Information Appliances

RT9187-10PQV, RT9187-11PQV, RT9187-32PQV, RT9187-33PQV

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Description
The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051.
All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD ³ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR.
The power consumption is max. 5.5 mW in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential.

PFeatures
*256 x 8-bit organization
*Standby mode
*Compatible with the NMOS and CMOS versions of the microprocessor/microcontroller families
SAB 8086, SAB 8051
*Very low power dissipation
*Data retention up to VDD ³ 1 V
*Three different chip select inputs for two chip select modes
*No increasing power consumption in standby mode if the control inputs are on undefined potential
*Temperature range – 40 to 110 °C

SAE81C52P, SAE81C52G

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General Description
The TC850 is a monolithic CMOS A/D converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per second up to 40 per second). Faster conversion speed is especially welcome in systems with human interface, such as digital scales.
The TC850 incorporates an ADC and a μP-compatible digital interface. Only a voltage reference and a few, noncritical, passive components are required to form a complete 15-bit plus sign ADC. CMOS processing provides the TC850 with high-impedance, differential inputs. Input bias current is typically only 30 pA, permitting direct interface to sensors. Input sensitivity of 100 μV per Least Significant bit (LSb) eliminates the need for precision external amplifiers. The internal amplifiers are auto-zeroed, ensuring a zero digital output, with 0V analog input. Zero adjustment potentiometers or calibrations are not required.
The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible while outputs are TTL/CMOS compatible. Chip-enable and byte-select inputs, combined with an end-of-conversion output, ensures easy interfacing to a wide variety of microprocessors.
Conversions can be performed continuously or on command. In Continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required.
Operating from ±5V supplies, the TC850 dissipates only 20 mΩ. The TC850 is packaged in a 40-pin plastic or ceramic dual-in-line package (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package.

Features
*15-bit Resolution Plus Sign Bit
*Up to 40 Conversions per Second
*Integrating ADC Technique:
-Monotonic
-High Noise Immunity
-Auto-Zeroed Amplifiers Eliminate Offset Trimming
*Wide Dynamic Range: 96 dB
*Low Input Bias Current: 30 pA
*Low Input Noise: 30 μVP-P
*Sensitivity: 100 μV
*Flexible Operational Control
*Continuous or On Demand Conversions
*Data Valid Output
*Bus Compatible, 3-State Data Outputs:
-8-Bit Data Bus
-Simple μP Interface
-Two Chip Enables
-Read ADC Result Like Memory
*± 5V Power Supply Operation: 20 mΩ
*40-Pin Dual-in-Line or 44-Pin PLCC Packages

Applications
*Precision Analog Signal Processor
*Precision Sensor Interface
*High Accuracy DC Measurements

TC850CPL, TC850IJL, TC850CLW, TC850ILW

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DESCRIPTION
This registered bus exchanger is built using advanced dual metal CMOS technology. The ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA input allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction
changes with CLK.
The ALVCH16270 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The ALVCH16270 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

FEATURES
*0.5 MICRON CMOS Technology
*Typical tSK(o) (Output Skew) < 250ps
*ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
*VCC = 3.3V ± 0.3V, Normal Range
*VCC = 2.7V to 3.6V, Extended Range
*VCC = 2.5V ± 0.2V
*CMOS power levels (0.4μ W typ. static)
*Rail-to-Rail output swing for increased noise margin
*Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES
*High Output Drivers: ±24mA
*Suitable for heavy loads

APPLICATIONS
*3.3V high speed systems
*3.3V and lower voltage computing systems

IDT74ALVCH16270PV, IDT74ALVCH16270PA, IDT74ALVCH16270PF

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Description
The Hitachi HM628512 is a 4-Mbit static RAM organized 512-kword ´ 8-bit. It realizes igher density, higher performance and low power consumption by employing 0.5 mm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. LP-version is suitable for battery backup system.

Features
*High speed: Fast access time:
-55/65/70 ns (max)
*Low power
-Standby: 10 mW (typ) (L/L-SL version)
-Operation: 75 mW (typ) (f = 1 MHz)
*Single 5 V supply
*Completely static memory No clock or timing strobe required
*Equal access and cycle times
*Common data input and output: Three state output
*Directly TTL compatible: All inputs and outputs
*Capability of battery backup operation (L/L-SL version)

HM628512P-5, HM628512P-7, HM628512LP-5, HM628512LP-7A, HM628512LP-7

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Description
The LUPA 1300-2 is a highly integrated SXGA high speed, high sensitivity CMOS image sensor targeted at various high speed machine vision and industrial monitoring applications. The sensor runs at 500fps and features triggered and pipelined shutter modes. The sensor packs 24 parallel 10-bit A/D converters with an aggregate conversion rate of 740 MSPS.
On-chip digital column FPN correction allows the sensor to output ready-to-use image data for all but the most demanding applications. In order to allow simple and reliable system integration, the 13 channel 8 Gbps LVDS serial link protocol supports per channel skew correction and serial link integrity monitoring. Peak responsivity of the 14x14um 6T pixel is 7350
V.m2/W.s. Dynamic range is measured to be 57dB. In full frame video mode, the sensor consumes 1.2W from a 2.5V power supply. The sensors integrates A/D conversion, on-chip timing for a wide range of operating modes and features an LVDS interface for easy system integration. By removing the visually highly disturbing column patterned noise, this sensor allows building a camera without having to perform any off-line correction or the need for any memory making this sensor highly suitable for lower cost applications. Moreover, since the on-chip column FPN correction is more reliable than an off-line correction as it is intrinsically compensated for supply and temperature variations, this sensor also allows to build reliable high-end camera's without having to worry about column FPN appearing in environments with highly varying ambient temperatures.
The sensor requires only one master clock for operation up to 500 fps. It is housed in a 168-pin ceramic μPGA package.
The LUPA 1300-2 is available in a monochrome version or Bayer (RGB) patterned color filter array and is available with and without glass.

Features
*1280 x 1024 active pixels
*14 μm X 14 μm square pixels
*1" optical format
*Monochrome or color digital output
*500 fps frame rate
*On-chip 10-bit ADCs
*12 LVDS serial outputs
*Random programmable ROI readout
*Pipelined, Triggered and Snapshot shutter
*On-chip column FPN correction
*Serial to Parallel Interface (SPI)
*Limited supplies: Nominal 2.5V (some supplies require 3.3V)
*0°C to 70°C operational temperature range
*168-pin uPGA package
*Power dissipation: 1.2W

Applications
*High speed machine vision
*Motion analysis
*Intelligent traffic system
*Medical imaging
*Industrial imaging

CYIL2SM1300AA-GDCES, CYIL2SM1300AA-GWCES, CYIL2SC1300AA-GDCES, CYIL2SC1300AA-GWCES
TAG CMOS, Sensor

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General Description
The PEEL™22CV10A is a Programmable Electrically Erasable Logic (PEEL™) device providing an attractive alternative to ordinary PLDs. The PEEL™22CV10A offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 1), with speeds ranging from 7ns to 25ns and with power consumption as low as 30mA. EE-reprogrammability provides the conve- nience of instant reprogramming for development and a reusable production inventory, minimizing the impact of programming changes or errors. EE-reprogrammability also improves factory testability, thus ensuring the highest quality possible. The PEEL™22CV10A is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by using the “+” software/programming option (i.e., 22CV10A+ & 22CV10A++). The additional macrocell configurations allow more logic to be put into every design. Programming and development support for the PEEL™22CV10A are provided by popular third-party programmers and development software. Anachip also offers free PLACE development software.

Features
*High Speed/Low Power
-Speeds ranging from 7ns to 25ns
-Power as low as 30mA at 25MHz
*Electrically Erasable Technology
-Superior factory testing
-Reprogrammable in plastic package
-Reduces retrofit and development costs
*Development/Programmer Support
-Third party software and programmers
-Anachip PLACE Development Software
*Architectural Flexibility
-132 product term X 44 input AND array
-Up to 22 inputs and 10 outputs
-Up to 12 configurations per macrocell
-Synchronous preset, asynchronous clear
-Independent output enables
-24-pin DIP/SOIC/TSSOP and 28-pin PLCC
*Application Versatility
-Replaces random logic
-Pin and JEDEC compatible with 22V10
-Enhanced Architecture fits more logic than ordinary PLDs

22CV10A-10, 22CV10A-15, 22CV10A-25

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GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The device is available in windowed ceramic DIP packages and plastic one-time programmable (OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor
system.
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 100 mW in active mode, and 50 μW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 μs pulses) resulting in typical programming time of 1 minute.

DISTINCTIVE CHARACTERISTICS
*Fast access time
-Available in speed options as fast as 90 ns
*Low power consumption
-<10 μA typical CMOS standby current
*JEDEC-approved pinout
-Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
-Easy upgrade from 28-pin JEDEC EPROMs
*Single +5 V power supply
*±10% power supply tolerance standard
*100% Flashrite™ programming
-Typical programming time of 1 minute
*Latch-up protected to 100 mA from –1 V to VCC + 1 V
*High noise immunity
*Compact 32-pin DIP, PDIP, PLCC packages

AM29F400BT-45EC0, AM29F400BB-45EC0, AM29F400BT-45FC0

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Functional description
The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation
without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 8 bits
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*One chip select plus one Output Enable pin
*Bidirectional data inputs and outputs
*TTL-compatible
*28-pin JEDEC standard packages
-300 mil SOJ
-8 × 13.4 mm TSOP
-300 mil PDIP
*ESD protection ≥ 2000 volts

AS7C256B-12PIN, AS7C256B-12JIN, AS7C256B-12TIN
TAG CMOS, SRAM

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