DESCRIPTION
The STK25C48 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. The nvSRAM can be used in place of existing 2K x 8 SRAMs and also matches the pinout of 2K x 8 battery-backed SRAMs, EPROMs and EEPROMs, allowing direct substitution while enhancing performance. No support circuitry is required for microprocessor interfacing.

FEATURES
*Nonvolatile Storage without Battery Problems
*Directly Replaces 2K x 8 Static RAM, Battery- Backed RAM or EEPROMs
*25ns, 35ns and 45ns Access Times
*STORE to Nonvolatile Elements Initiated by AutoStore™ on Power Down
*RECALL to SRAM Initiated by Power Restore
*10mA Typical ICC at 200ns Cycle Time
*Unlimited READ, WRITE and RECALL Cycles
*1,000,000 STORE Cycles to Nonvolatile Elements
*100-Year Data Retention over Full Industrial Temperature Range
*Commercial and Industrial Temperatures
*24-Pin 600 PDIP Package

STK22C48-WF25I, STK22C48-W25I, STK22C48-WF45I, STK22C48-W45I

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Outline
This open drain output system reset IC, developed using the CMOS process. Super low consumption current of 1.0μA typ. (PST3810 ~ PST3819) has been achieved through use of the CMOS process. Also, detection voltage is high precision detection of ±2%.

Features
*Super low consumption current 1.0μA typ. (when VDD = (-VDET) + 2.0V) PST3810 ~ PST3819
*High precision detection voltage ±2%
*Operating range 0.7 ~ 10V
*Wide operating temperature range -30 ~ +85°C
*Detection voltage 0.9 ~ 6.0V (0.1V step)

Applications
*Microcomputer, CPU, MPU reset circuits
*Logic circuit reset circuits
*Battery voltage check circuits
*Back-up circuit switching circuits
*Level detection circuits

PST3809, PST3810, PST3811, PST3812, PST3813, PST3814, PST3815, PST3816

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General Description
The RT9004 is designed for portable RF and wireless applications with demanding performance and space requirements. The RT9004 performance is optimized for battery-powered systems to deliver ultra low noise and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The RT9004 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices. The RT9004 consumes less than 0.01uA in shutdown mode and has fast turn-on time less than 50us. RT9004 is short circuit thermal folded back protected. RT9004 lowers its OTP trip point from 165°C to 110°C when output short circuit occurs (VOUT < 0.4V) providing maximum safety to end users. The other features include ultra low dropout voltage, high output accuracy, current limiting protection, and high ripple rejection ratio. Available in the VDFN-10L 3x3 and WDFN-10L 3x3 packages, the RT9004 also offers custom voltage, range of 1.5V to 3.5V with 0.1V per step.

Features
*Short Circuit Thermal Folded Back Protection
*Low-Noise for RF Application
*Fast Response in Line/Load Transient
*Quick Start-Up (Typically 50us)
*Low Dropout : 220mV @ 300mA
*Wide Operating Voltage Ranges : 2.5V to 5.5V
*TTL-Logic-Controlled Shutdown Input
*Low Temperature Coefficient
*Thermal Shutdown Protection
*Only 1uF Output Capacitor Required for Stability
*High Power Supply Rejection Ratio
*Custom Voltage Available
*Small 10-Lead VDFN and WDFN Packages
*RoHS Compliant and 100% Lead (Pb)-Free

Applications
*CDMA/GSM Cellular Handsets
*Battery-Powered Equipment
*Laptop, Palmtops, Notebook Computers
*Hand-Held Instruments
*PCMCIA Cards
*Portable Information Appliances

RT9004APQV, RT9004BPQV, RT9004CPQV, RT9004DPQV, RT9004EPQV

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GENERAL DESCRIPTION
The W39L020 is a 2Mbit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. For flexible erase capability, the 2Mbits of data are divided into 4 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39L020 results in fast program/erase operations with extremely low current consum ption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.

FEATURES
*Single 3.3-volt operations
-3.3-volt Read
-3.3-volt Erase
-3.3-volt Program
*Fast Program operation:
-Byte-by-Byte programming: 50 μS (max.)
*Fast Erase operation:
-Chip Erase cycle time: 100 mS (max.)
-Sector Erase cycle time: 25mS (max.)
-Page Erase cycle time: 25mS (max.)
*Read access time: 70/90 nS
*4 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes
*Any individual sector or page can be erased
*Hardware protection:
-Optional 16K byte or 64K byte Top/Bottom Boot Block with lockout protection
*Flexible 4K-page size can be used as Parameter Blocks
*Typical program/erase cycles: 1K/10K
*Twenty-year data retention
*Low power consumption
-Active current: 10 mA (typ.)
-Standby current: 5 μA (typ.)
*End of program detection
-Software method: Toggle bit/Data polling
*TTL compatible I/O
*JEDEC standard byte-wide pinouts
*Available packages: 32L PLCC, 32L TSOP (8 x 20 mm) and 32L STSOP (8 x 14 mm)

W39L020P-70, W39L020P-90, W39L020T-70, W39L020T-90, W39L020Q-70

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DESCRIPTION
The Simtek STK16CA8 is a fast static RAM with a nonvolatile element in each static memory cell. The embedded nonvolatile elements incorporate Simtek’s QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down or under software control. An internal capacitor guarantees the STORE operation, even under extreme power-down slew rates or loss of power from “hot swapping”. Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16CA8 is pin-compatible with 128k x 8 SRAMs and batterybacked SRAMs, allowing direct substitution while providing superior performance.

FEATURES
*25ns, 35ns and 45ns Access Times
*Directly Replaces 128K x 8 Static RAM, Battery-Backed RAM or EEPROM
*Transparent Data Save on Power Down
*STORE to QuantumTrap™ Nonvolatile Elements is Initiated by Software or AutoStore-Plus™on Power Down
*RECALL to SRAM Initiated by Software or Power Restore
*5mA Typical ICC at 200ns Cycle Time
*Unlimited READ and WRITE Cycles to SRAM
*100-Year Data Retention to Quantum Trap
*Single 3V +20%, -10% Operation
*Commercial and Industrial Temperatures
*32-Pin DIP Package

STK16CA8-WF45I, STK16CA8-W45I, STK16CA8-WF35I, STK16CA8-W35I

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GENERAL DESCRIPTION
The MP7541B is a pin-compatible replacement which offers superior performance in latch-up and ESD protection versus the comparable 7541 and 7541A. The high ESD protection will reduce failures caused by mishandling. These devices are manufactured using patented advanced thin film resistors on a double metal CMOS process which result in ultra stable thin film and superior long life reliability and stability. The MP7541B incorporates a bit decoding technique yielding lower glitch, higherspeed and excellent accuracy over temperature and time. The MP7541B’s outstanding features are:
Stability: Both Integral Non-Linearity (INL) and Differential-Non-Linearity (DNL) are rated at 0.2 ppm/°C maximum. Monotonicity is guaranteed over the entire temperature range. Gain Temperature Coefficient (TCGE) is 2.0 ppm/°C typical.
Lower Sensitivity to Output Amplifier Offset: Multiplying DACs provide an output current into a virtual ground of the output op amp. Additional linearity error caused by the op amp is reduced by a factor of 3 in the MP7541B versus conventional R-2R DACs.

FEATURES
*ESD Protection: 2000 V Minimum
*Full Four Quadrant Multiplication
*Low Glitch Energy
*12-Bit Linearity (End-Point)
*Guaranteed Monotonic. All Grades. All Temperatures.
*TTL/5 V CMOS Compatible
*Stable, More Accurate Segmented Architecture
–2.0 ppm/°C Typ. Gain Error Tempco
–0.2 ppm/°C Max. Linearity Tempco
–Lowest Sensitivity to Output Amplifier Offset
*Latch-Up Free

APPLICATIONS
*Industrial Automation
*Automatic Test Equipment
*Disk Drive Servo Systems
*Digital/Synchro Conversion
*Programmable Gain Amplifiers
*Ratiometric A/D Conversion
*Function Generation
*Digitally Controlled Filters

MP7541BSD, MP7541BTD, MP7541BJN, MP7541BKN, MP7541BJS, MP7541BKS

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General Description
The A29L320A is a 32Mbit, 3.3 volt-only Flash memory organized as 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L320A is offered in 48-ball TFBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L320A can also be programmed in standard EPROM programmers.
The A29L320A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L320A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L320A also offers the ability to program in the Erase Suspend mode. The standard A29L320A offers access times of 70,80,90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L320A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L320A is fully erased when shipped from the factory.
The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
-Regulated voltage range: 2.7 to 3.6 volt read and write operations for compatibility with high performance 3 volt microprocessors
*Access times:
-70/80/90/120 (max.)
*Current:
-2mA active read current at 1MHz
-10mA active read current at 5MHz
-20 mA typical program/erase current
-500 nA typical CMOS standby or Automatic Sleep Mode current
*Flexible sector architecture
-Eight 8 Kbyte sectors
-Sixty-three 64 kbyte sectors
-Any combination of sectors can be erased
-Supports full chip erase
-Sector protection:
*Unlock Bypass Program Command
-Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
-Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
-Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
-Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
-Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
-Pinout and software compatible with single-power-supply Flash memory standard
-Superior inadvertent write protection
*Data Polling and toggle bits
-Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
-Provides a hardware method of detecting completion of program or erase operations
*Erase Suspend/Erase Resume
-Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
-Hardware method to reset the device to reading array data
*WP /ACC input pin
-Write protect ( WP ) function allows protection of two outermost boot sectors, regardless of sector protect status
-Acceleration (ACC) function provides accelerated program times
*Hardware/Software temporary sector block unprotect command allows code changes in previously locked sectors
*Hardware/Software sector protect/unprotect command
*Package options
-48-pin TSOP (I) or 48-ball TFBGA
-All Pb-free (Lead-free) products are RoHS compliant

A29L320ATV-70, A29L320ATV-70U, A29L320ATV-70I, A29L320ATV-70F

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Functional description
The AS7C513C is a 5V high-performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C513C is packaged in common industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 16 bits
*Center power and ground pins for low noise
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*Easy memory expansion with CE, OE inputs
*TTL-compatible, three-state I/O
*Upper and Lower byte pin
*JEDEC standard packaging
-44-pin 400 mil SOJ
-44-pin TSOP 2
*ESD protection ≥ 2000 volts

AS7C513C-12JIN, AS7C513C-12TIN
TAG CMOS, SRAM

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DESCRIPTION
The 16-bit wide UT54ACS164245S MultiPurpose transceiver is built using UTMC’s Commercial RadHardTM epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS164245S transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, and cold sparing. With VDD equal to zero volts, the UT54ACS164245S outputs and inputs present a minimum impedance of 1MW making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS164245S well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS164245S enables system designers to interface 3.3 volt CMOS compatible components with 5 volt CMOS components. For voltage translation, the A port interfaces with the 3.3 volt bus; the B port interfaces with the 5 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver.

FEATURES
*Voltage translation
-5V bus to 3.3V bus
-3.3V bus to 5V bus
*Cold sparing
-1MW minimum input impedance power-off
*0.6mm Commercial RadHardTM CMOS
-Total dose: 100K rad(Si)
-Single Event Latchup immune
*High speed, low power consumption
*Schmitt trigger inputs to filter noisy signals
*Available QML Q or V processes
*Standard Microcircuit Drawing 5962-98580
*Package:
-48-lead flatpack, 25 mil pitch (.390 x .640)

UT54ACS164245SCC, UT54ACS164245SPC, UT54ACS164245SWC

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GENERAL DESCRIPTION
The ALD555 timer is a high performance monolithic timing circuit built with advanced silicon gate CMOS technology. It offers the benefits of high input impedance, thereby allowing smaller timing capacitors and longer timing cycle; high speed, with typical cycle time of 500ns; low power dissipation for battery operated environment; reduced supply current spikes, allowing smaller and lower cost decoupling capacitors. It is capable of producing accurate time delays and oscillations in both monostable and astable operation. It operates in the one-shot (monostable) mode or 50% duty cycle free running oscillation mode with a single resistor and one capacitor. The inputs and outputs are fully compatible with CMOS, NMOS or TTL logic.
There are three matched internal resistors (approximately 200KW each) that set the threshold and trigger levels at two-thirds and one-third respectively of V+. These levels can be adjusted by using the control terminal (pin 5). When the trigger input is below the trigger level, the output is in the high state and sourcing 2mA. When threshold input is above the threshold level at the same time the trigger input is above the trigger level, the internal flip-flop is reset, the output goes to the low state and sinks up to 10mA. The reset input overrides all other inputs and when it is active (reset voltage less than 1V), the output is in the low state.

FEATURES
*Functional equivalent to NE555 with greatly expanded high and low frequency ranges
*High speed, low power, monolithic CMOS technology
*Low supply current 100mA typical
*Extremely low trigger, threshold and reset currents -- 1pA typical
*High speed operation -- 2MHz oscillation
*Low operating supply voltage 2 to 12V
*Operates in both monostable and astable modes
*Fixed 50% duty cycle or adjustable duty cycle CMOS, NMOS and TTL compatible input/output
*High discharge sinking current (80mA)
*Low supply current spikes

APPLICATIONS
*High speed one-shot (monostable) pulse generation
*Precision timing
*Sequential timing
*Long delay timer
*Pulse width and pulse position modulation
*Missing pulse detector
*Frequency divider

ALD555DA, ALD555SA, ALD555PA
TAG CMOS

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