The TC74VHC9541 is an ultra-high-speed octal Schmitt buffer fabricated using silicon-gate CMOS technology. The TC74VHC9541 combines low power consumption of CMOS with Schottky TTL speeds.
The outputs can be put in the high-impedance state by placing a logic HIGH on the Enable (G) input. The CONT input determines the logical inversion of data. A logic LOW on the CONT input configures the TC74VHC9541 as an inverter; a logic HIGH on the CONT input configures the TC74VHC9541 as a buffer.
All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHC9541 is capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity.
Additionally, all the inputs have a newly developed protection circuit without a diode returned to VCC. This enables the inputs to be tolerant of up to 5 volts even when power supply is down. The input power-down protection capability makes the TC74VHC9541 ideal for a wide range of applications, such as interfacing between different voltages, voltage translation from 5 V to 3 V and battery back-up circuits.

*High speed: tpd = 5.0 ns (typ.) (VCC = 5 V)
*Low supply current: ICC = 4 μA (max) (Ta = 25°C)
*High noise immunity: VNIH = VNIL = 28% VCC (min)
*All inputs are provided with power-down protection.
*Symmetrical rise and fall delays: tpLH ≈ tpHL
*Wide operating voltage range: VCC (opr) = 2 to 5.5 V
*Pin-compatible with TC74VHC540 and TC74VHC541

TC74VHC9541FT, TC74VHC9541FK
TAG Buffer, Octal

댓글을 달아 주세요 Comment

The IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

*Guaranteed Low Skew < 25ps (max)
*Very low duty cycle distortion < 125ps (max)
*High speed propagation delay < 1.75ns (max)
*Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
*Up to 1GHz operation
*Selectable inputs
*Hot insertable and over-voltage tolerant inputs
*3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
*Selectable differential inputs to six LVDS outputs
*Power-down mode
*2.5V VDD
*Available in VFQFPN package

*Clock distribution

TAG Buffer, Clock, LVDS

댓글을 달아 주세요 Comment

The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.

*2.5V or 3.3V operation
*200-MHz clock support
*LVPECL or LVCMOS/LVTTL clock input
*LVCMOS/LVTTL compatible outputs
*15 clock outputs: drive up to 30 clock lines
*1X and 1/2X configurable outputs
*Output three-state control
*350 ps maximum output-to-output skew
*Pin compatible with MPC949, MPC9449
*Available in Commercial and Industrial temperature range
*52-pin TQFP package

CY29949AXI, CY29949AXIT, CY29949AXC, CY29949AXCT

댓글을 달아 주세요 Comment

General Description
This device contains six independent gates each of which performs a buffer function.
The open-collector outputs require external pull-up resistors for proper logical operation.

TAG Buffer, HEX

댓글을 달아 주세요 Comment

The AZ10/100LVEL11 is a differential 1:2 fanout gate.
The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open input conditions.
If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

*265ps Propagation Delay
*5ps Skew Between Outputs
*High Bandwidth Output Transitions
*Internal Input Pulldown Resistors
*Operating Range of 3.0V to 5.5V
*Direct Replacement for ON Semi
-MC100LVEL11, MC10EL11
-& MC100EL11
*Transistor Count = 51


TAG Buffer

댓글을 달아 주세요 Comment

The MC74VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC244 is a noninverting 3–state buffer, and has two active–low output enables.
This device is designed to be used with 3–state memory address drivers, etc.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.


* High Speed: tPD = 3.9ns (Typ) at VCC = 5V
* Low Power Dissipation: ICC = 4mA (Max) at TA = 25°C
* High Noise Immunity: VNIH = VNIL = 28% VCC
* Power Down Protection Provided on Inputs
* Balanced Propagation Delays
* Designed for 2V to 5.5V Operating Range
* Low Noise: VOLP = 0.9V (Max)
* Pin and Function Compatible with Other Standard Logic Families
* Latchup Performance Exceeds 300mA
* ESD Performance: HBM > 2000V; Machine Model > 200V
* Chip Complexity: 136 FETs or 34 Equivalent Gates

TAG Buffer

댓글을 달아 주세요 Comment

PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCIExpress clock generator for Intel server chipsets.
The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is LOW.
The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.
When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated.
When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

* Phase jitter fi lter for PCIe application
* Eight Pairs of Differential Clocks
* Low skew < 50ps
* Low Cycle-to-cycle jitter < 50ps
* Output Enable for all outputs
* Outputs Tristate control via SMBus
* Power Management Control
* Programmable PLL Bandwidth
* PLL or Fanout operation
* 3.3V Operation
* Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)

TAG Buffer, Clock, HCSL, PCI

댓글을 달아 주세요 Comment

 The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package.
Output is disabled when the associated output enable (OE) input is low.
To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver.
Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.

* The basic gate function is lined up as hitachi uni logic series.
* Supplied on emboss taping for high speed automatic mounting.
* TTL compatible input level.
- Supply voltage range : 4.5 to 5.5 V
- Operating temperature range : –40 to +85°C
* All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
- All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
* Output current ±12 mA (@VCC = 4.5 V to 5.5 V)
* All the logical input has hysteresis voltage for the slow transition.

TAG Buffer, Gate

댓글을 달아 주세요 Comment

 The Cypress W40S11-02 is a low-voltage, ten-output clock buffer.
Output buffer impedance is approximately 15Ω, which is ideal for driving SDRAM DIMMs.

* Ten skew-controlled CMOS outputs (SDRAM0:9)
* Supports two SDRAM DIMMs
* Ideal for high-performance systems designed around Intel®’s latest mobile chip set
* SMBus serial configuration interface
* Skew between any two outputs is less than 250 ps
* 1 to 5 ns propagation delay
* DC to 133-MHz operation
* Single 3.3V supply voltage
* Low power CMOS design packaged in a 28-pin, 209-mil SSOP (Shrink Small Outline Package)

Key Specifications
* Supply Voltages: ...........................................VDD = 3.3V±5%
* Operating Temperature:.................................... 0°C to +70°C
* Input Threshold:...................................................1.5V typical
* Maximum Input Voltage: ...................................... VDD + 0.5V
* Input Frequency:............................................... 0 to 133 MHz
* BUF_IN to SDRAM0:9 Propagation Delay:........ 1.0 to 5.0 ns
* Output Edge Rate: ................................................. >1.5 V/ns
* Output Skew: ............................................................ ±250 ps
* Output Duty Cycle:...................................45/55% worst case
* Output Impedance: ....................................... 15 ohms typical
* Output Type: ............................................... CMOS rail-to-rail


댓글을 달아 주세요 Comment

The UT7R995/UT7R995C is a low-voltage, low-power, eightoutput, 6-to-200 MHz clock driver.
It features output phase programmability which is necessary to optimize the timing of high performance microprocessor and communication systems.
The user programs both the frequency and the phase of the output banks through nF[1:0] and DS[1:0] pins.
The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock.
Connect any one of the outputs to the feedback input to achieve different reference frequency multiplication and division ratios.
The devices also feature split output bank power supplies that enable banks 1 & 2, bank 3, and bank 4 to operate at a different power supply levels.
The ternary PE/HD pin controls the synchronization of output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers.
The UT7R995 and UT7R995C both interface to a digital clock while the UT7R995C will also interface to a quartz crystal.

* +3.3V Core Power Supply
* +2.5V or +3.3V Clock Output Power Supply
- Independent Clock Output Bank Power Supplies
* Output frequency range: 6 MHz to 200 MHz
* Bank pair output-output skew < 100 ps
* Cycle-cycle jitter < 50 ps
* 50% ± 2% maximum output duty cycle at 100MHz
* Eight LVTTL outputs with selectable drive strength
* Selectable positive- or negative-edge synchronization
* Selectable phase-locked loop (PLL) frequency range and lock indicator
* Phase adjustments in 625 to 1300 ps steps up to ± 7.8 ns
* (1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios
* Compatible with Spread-Spectrum reference clocks
* Power-down mode
* Selectable reference input divider
* Radiation performance
- Total-dose tolerance: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm2/mg
- SEU Immune to a LET of 109 MeV-cm2/mg
* Military temperature range: -55oC to +125oC
* Extended industrial temp: -40oC to +125oC
* Packaging options:
- 48-Lead Ceramic Flatpack
* Standard Microcircuit Drawing: 5962-05214
- QML-Q and QML-V compliant part


댓글을 달아 주세요 Comment