GENERAL DESCRIPTION
 W9864G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits.
W9864G6IH delivers a data bandwidth of up to 200M words per second.
For different application, W9864G6IH is sorted into the following speed grades: -5, -6, -7/-7S. The -5 parts can run up to 200MHz/CL3.
The -6 parts can run up to 166MHz/CL3.
The -7/-7S parts can run up to 143MHz/CL3.
And the grade of -7S with tRP = 18nS.
Accesses to the SDRAM are burst oriented.
Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the SDRAM internal counter in burst operation.
Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance.
W9864G6IH is ideal for main memory in high performance applications.

FEATURES
* 3.3V± 0.3V for -5/-6 speed grades power supply
* 2. 7V~3.6V for -7/-7S speed grades power supply
* 1,048,576 words × 4 banks × 16 bits organization
* Self Refresh Current: Standard and Low Power
* CAS Latency: 2 & 3
* Burst Length: 1, 2, 4, 8 and full page
* Sequential and Interleave Burst
* Byte data controlled by LDQM, UDQM
* Auto-precharge and controlled precharge
* Burst read, single write operation
* 4K refresh cycles/64mS
* Interface: LVTTL
* Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant

W9864G6IH-5
W9864G6IH-6
W9864G6IH-7
W9864G6IH-7S

TAG Bank, SDRAM

Trackback :: http://datasheetblog.com/trackback/1650

댓글을 달아 주세요 Comment

Description
 The TM54S816T is organized as 4-bank x 2097152-word x 16-bit(8Mx16), fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features
* Package: 400-mil 54-pin TSOP(II)
* JEDEC PC133/PC100 compatible
* Single 3.3V Power Supply
* LVTTL Signal Compatible
* Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4, 8 & full page)
- Burst type (Sequential & Interleave)
* Burst read/write and burst read/single write operations capability
* Byte control(DQML and DQMU)
* Auto and Self Refresh
* 64ms refresh period (4K Refresh)
* 12-Row x 9-Column organization
* 4-Bank operation controlled by BA1,BA0
* Pin36 and 40 are “No Connected”
* Fully synchronous operation referenced to clock rising edge

Trackback :: http://datasheetblog.com/trackback/1584

댓글을 달아 주세요 Comment

General Description
ADD8608A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 8,392,608 words x 8 bits x 4 banks, Synchronous design allows precise cycle control the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and CK.
 Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications.

Features
•2.5V for VDDQ power supply
•SSTL_2 interface
•MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave)
•4 banks operation
•Differential clock input (CK, /CK) operation
•Double data rate interface
•Auto & Self refresh
•8192 refresh cycle
•DQM for masking
•Package:66-pins 400 mil TSOP-Type II

ADD8608A8A-75BA
ADD8608A8A-75B
TAG Bank, Data, SDRAM

Trackback :: http://datasheetblog.com/trackback/681

댓글을 달아 주세요 Comment