Pericom Semiconductor’s PI3HDMI series of switch circuits are targeted for high-resolution video networks that are based on DVI/HDMI standards, and TMDS signal processing. The
PI3HDMI412FT-B is an 8- to 4-Channel Mux/DeMux Switch. The device multiplexes differential signals to one of two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. It is designed for low bit-to-bit skew and high channel-to-channel noise isolation.
The allowable data rate of 5.0Gbps provides the resolution required by the next generation HDTV and PC graphics. Three differential channels are used for data (video signals for DVI or audio/video signals for HDMI), and one differential channel is used for Clock for decoding the TMDS signals at the outputs.
Due to its integrated pull-up resistors, the product has been designed specifi cally for applications where the part is used as a 2 to 1 mux, not 1 to 2 demux. Therefore, Pericom only recommends the part to be used as a 2 to 1 mux when dealing with HDMI signals. Even though the passive circuitry does not eliminate the bi-directional functionality, it is not ideal when used with HDMI signals. If DVI are used, either direction can be used.

*4-Differential Channel 2:1 Mux/DeMux
*HDMI 1.1, 1.2, and 1.3 compatible
*Allowable Data Rate: > 5.0 Gbps
*Supports both AC coupled and DC coupled signals
*Switching speed: 4ns
*Isolation: -40dB @ 2.0 Gbps
*Crosstalk: -31dB @ 2.0 Gbps
*ESD: Data bits @ 8kV contact, select bit @ 2kV HBM
*Low bit-to-bit skew
*Enable/Disable Time: 9ns
*Packaging (Pb-free & Green):
— 42-pin TQFN (ZH42)
— 48-pin BQSOP (B48)


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*-25db Non-Adjacent Channel Crosstalk at 1.65Gbps
*Low Signal Loss: -1.5dBg attenuation at 1.65Gbps
*Isolation Ground Between Channels
*Fast Turn-on/off Time (< 6ns)
*1.65Gbps Throughput
*8kV ESD Protection
*Low Skew: Intra-pair <90ps, Inter-pair < 150ps
*Low Power Consumption (1μA Maximum)

*XGA and 720p DVI and HDMI Video Source Selection

The FSHDMI08 is a wide-bandwidth switch designed for routing HDMI link data, clock, and the relevant DDC and CEC control signals that support the data rate up to 1.65Gbps per channel for UXGA resolution. Applications include LCD TVs, DVD, set-top boxes, and notebook designs with multiple digital video interfaces.
This switch allows the passage of HDMI link signals with ultra-low non-adjacent channel crosstalk and ultralow off isolation. This is critical to minimize ghost image between active video sources in video applications. The wide bandwidth of this switch allows the high-speed
differential signal to pass through with minimal additive skew and phase jitter. The pinout supports an HDMI Standard-A connector PCB layout.


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General Description
 The ADC14V155 is a high-performance CMOS analog-todigital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size.  
 This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes 951 mW of power at 155 MSPS.
 The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

 The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can be operated with an external reference. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable.
 A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. It is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.

■ 1.1 GHz Full Power Bandwidth
■ Internal sample-and-hold circuit
■ Low power consumption
■ Internal precision 1.0V reference
■ Single-ended or Differential clock modes
■ Clock Duty Cycle Stabilizer
■ Dual +3.3V and +1.8V supply operation (+/- 10%)
■ Power-down and Sleep modes
■ Offset binary or 2's complement output data format
■ LVDS outputs
■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

Key Specifications
- Resolution 14 Bits
- Conversion Rate 155 MSPS
- SNR (fIN = 70 MHz) 71.7 dBFS (typ)
- SFDR (fIN = 70 MHz) 86.9 dBFS (typ)
- ENOB (fIN = 70 MHz) 11.5 bits (typ)
- Full Power Bandwidth 1.1 GHz (typ)
- Power Consumption 951 mW (typ)

■ High IF Sampling Receivers
■ Wireless Base Station Receivers
■ Power Amplifier Linearization
■ Multi-carrier, Multi-mode Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Radar Systems


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