Description
The EP3102 is a monolithic integrated circuit that provide all the active functions for a step-down switching regulator, capable of driving a 2A load without additional transistor component. Requiring a minimum number of external component, the board space can be saved easily. The external shutdown function can be controlled by TTL logic level and then come into standby mode. The internal compensation makes feedback control have good line and load regulation without external design. Regarding protected function, thermal shutdown is to prevent over temperature operating from damage, and current limit is against over current operating of the output switch. The EP3102 operates at a switching frequency of 150KHz thus allowing smaller sized filter components than what would be needed with lower frequency switching regulators. Other features include a guaranteed +4% tolerance on output voltage under specified input voltage and output load conditions, and +15% on the oscillator frequency. The output version included fixed 3.3V, 5V, 12V, and an adjustable type. The package is available in a standard 8-lead SOP8.

Features
*3.3V, 5V, 12V and Adjustable Output Version
*Adjustable Version Output Voltage Range, 1.23V to 37V +4% Max over Line and Load Condition
*Input Voltage Range up to 40V
*Output Load Current: 2A
*150 KHz Fixed Frequency Internal Oscillator
*Voltage Mode Non-synchronous PWM Control
*Thermal-shutdown and Current-limit Protection
*ON/OFF Shutdown Control Input
*Low Power Standby Mode
*Built-in Switching Transistor on Chip
*SOP-8L package

Applications
*Simple High-efficiency Step-down (Buck) Regulator
*Efficient Pre-regulator for Linear Regulators
*On-card Switching Regulators
*Positive to Negative Converter
*Battery Charger

EP3102-S33R, EP3102-S50R, EP3102-S12R, EP3102-SR

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General Description
The a6402 MegaCore function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial communications channel.

Features
*a6402 MegaCore function implementing a universal asynchronous receiver/transmitter (UART)
*Optimized for FLEX® and MAX® architectures
*Uses approximately 162 FLEX logic elements (LEs)
*Programmable word length, stop bits, and parity
*Full duplex operation
*Includes status flags for parity, framing, and overrun errors
*Functionally based on the Harris HD-6402 device, except as noted in the “Variations & Clarifications” section on page 63

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Description
The IMP16C554 is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. A programmable baud rate generator is provided to select transmit and receive clock rates from 50Hz to 1.5MHz.
The IMP16C554 is an improved version of the IMP16C550 UART with higher operating speed and lower access time. The IMP16C554 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user’s requirements. The IMP16C554 provides internal loop-back capability for on board diagnostic testing.
The IMP16C554 is fabricated in an advanced 1.2u CMOS process to achieve low drain power and high speed requirements.

Key Features
*16 byte receive FIFO with error flags
*Modem control signal (CTS*, RTS*, DSR*, DTR*, RI* ,CD*)
*Programmable character lengths(5,6,7,8)
*Even, odd, or no parity bit generation and detection
*Status report register
*Independent transmit and receive control
*TLL compatible inputs. outputs
*Software compatible with Ei8250, 1Ei16C550
*460.8kHz transmit/receive operation with 7.372 MHz crystal or external clock source

IMP16C554-CJ68, IMP16C554-LJ68

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Description
The EP3101 series are monolithic integrated circuits that provide all the active functions for a step-down DC/DC converter, capable of driving a 3A load without additional transistor component. Requiring a minimum number of external components, the board space can be saved easily. The external shutdown function can be controlled by TTL logic level and then come into standby mode. The internal compensation makes feedback control have good line and load regulation without external design. Regarding protected function, thermal shutdown is to prevent over temperature operating from damage, and current limit is against over current operating of the output switch.
The EP3101 series operates at a switching frequency of 150KHz thus allowing smaller sized filter frequency switching regulators. Other features include a guaranteed ±4% tolerance on output voltage under specified input voltage and output load conditions, and ±15 % on the oscillator frequency. The output version includes fixes 3.3V, 5V, 12V, and an adjustable type. The packages are available in a standard 5-lead TO-220(T) package and a 5-lead TO-263(U)..

Features
*Output Voltage: 3.3V, 5V, 12V and Adjustable Output Version
*Adjustable Version Output Voltage Range, 1.23V to 37V ±4%
*150KHz±15% Fixed Switching Frequency
*Voltage Mode Asynchronous PWM Control
*Thermal-shutdown and Current-limit Protection
*ON/OFF Shutdown Control Input
*Operating Voltage can be up to 40V
*Output Load Current: 3A
*Low Power Standby Mode
*Built-in on Chip Switching Transistor
*TO263-5L and TO220-5L Packages

Applications
*Simple High-efficiency Step-down Regulator
*On-card Switching Regulators
*Positive to Negative Converter

EP3101-X33R, EP3101-X50R, EP3101-X12R, EP3101-XR

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Overview
The N08M1618L1A is an integrated memory device intended for non life-support medical
applications. This device is a 8 megabit memory organized as 524,288 words by 16 bits. The device is designed and fabricated using AMI Semiconductor’s advanced CMOS technology with reliability inhancements for medical users. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. This device is optimal for various applications where low-power is critical such as battery backup and hand-held devices.
The device can operate over a very wide temperature range of -40oC to +85oC and is available in a JEDEC standard BGA package.

Features
• Dual voltage for Optimum Performance:
Vccq - 2.3 to 3.6 Volts
Vcc - 1.4 to 2.2 Volts
• Very low standby current
0.5μA at 1.8V and 37 deg C
• Very low operating current
1.0mA at 1.8V and 1μs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1μs (Typical)
• Simple memory control
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
• Special Processing to reduce Soft Error Rate
(SER)
• Automatic power down to standby mode

N08M1618L1AB-85I     
N08M1618L1AD-85I

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*Reads and Writes Can Be Asynchronous or Coincident
*Organization:
– SN74ACT7200L – 256 × 9
– SN74ACT7201LA – 512 × 9
– SN74ACT7202LA – 1024 × 9
*Fast Data Access Times of 15 ns
*Read and Write Frequencies up to 40 MHz
*Bit-Width and Word-Depth Expansion
*Fully Compatible With the IDT7200/7201/7202
*Retransmit Capability
*Empty, Full, and Half-Full Flags
*TTL-Compatible Inputs
*Available in 28-Pin Plastic DIP (NP), Small-Outline (DV), and 32-Pin Plastic J-Leaded Chip-Carrier (RJ) Packages

description

The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address counters to provide data throughput on a first-in, first-out (FIFO) basis. Write and read operations are independent and can be asynchronous or coincident. Empty and full status flags prevent underflow and overflow of memory, and depth-expansion logic allows combining the storage cells of two or more devices into one FIFO.

Word-width expansion is also possible. Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R) input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of 15 ns.

These devices are particularly suited for providing a data channel between two buses operating at asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in dataacquisition systems, temporary storage elements between buses and magnetic or optical memories, and queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for retransmitting previously read data when a device is not used in depth expansion.

The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C to 70°C.

SN74ACT7200L
SN74ACT7201LA
SN74ACT7202LA


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Description
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and
any error conditions encountered. The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216–1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.

Feature
· Integrated Asynchronous Communications Element
· Consists of Four Improved TL16C550 ACEs Plus Steering Logic
· In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
· In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data
· Up to 16-MHz Clock Rate for up to 1-M baud Operation
· Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (216–1) and Generate an Internal 16 × Clock
· Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
· Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
· Fully Programmable Serial Interface Characteristics:
  – 5-, 6-, 7-, or 8-Bit Characters
  – Even-, Odd-, or No-Parity Bit
  – 1-, 1 1/2-, or 2-Stop Bit Generation
  – Baud Generation (DC to 1-Mbit Per Second)
· False Start Bit Detection
· Complete Status Reporting Capabilities
· Line Break Generation and Detection
· Internal Diagnostic Capabilities:
  – Loopback Controls for Communications Link Fault Isolation
  – Break, Parity, Overrun, Framing Error Simulation
· Fully Prioritized Interrupt System Controls
· Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
· 3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

TL16C554, TL16C554I, TL16C554FN, TL16C554IFN, TL16C554PN, TL16C554IPN

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