The MC13028A is a third generation C–QUAM stereo decoder targeted for use in low voltage, low cost AM/FM E.T.R. radio applications. Advanced features include a signal quality detector that analyzes signal strength, signal to noise ratio, and stereo pilot tone before switching to the stereo mode. A “blend function” much like FM stereo has been added to improve the transition from mono to stereo. The audio output level is adjustable to allow easy interface with a variety of AM/FM tuner chips. The external components have been minimized to keep the total system cost low.

*Adjustable Audio Output Level
*Stereo Blend Function
*Stereo Threshold Adjustment
*Operation from 2.2 V to 12 V Supply
*Precision Pilot Tone Detector
*Forced Mono Function
*Single Pinout VCO
*IF Amplifier with IF AGC Circuit
*VCO Shutdown Mode at Weak Signal Condition

MC13028AD, MC13028AP

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General Description
 The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs.
The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a 128-pin package.
This is space saving solution on the motherboard resulting in lower cost.
The LPC47M172 also provides 13 general purpose pins, which offer flexibility to the system designer, and two Fan Tachometer Inputs.
The LPC47M172’s LPC interface supports LPC I/O and DMA cycles.
The LPC47M172 includes complete legacy I/O: a keyboard interface with AMITM BIOS; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP.
The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data overflow and underflow protection.
The SMSC’s patented advanced digital data separator allows for ease of testing and use.
The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP.
The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake up events as well as PME support.
The PCC supports multiple low power-down modes.
The LPC47M172 is ACPI 1.0b/2.0 compatible.
The Motherboard GLUE logic includes various power management logic; including generation of nRSMRST, Power OK signal generation, 5V main and standby reference generation.
There are also three LEDs to indicate power status and hard drive activity.
The translation circuit converts 3.3V signals to 5V signals.
Also included is SMBus main power well to resume power well isolation circuitry.
The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a).
The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through the internal configuration registers.
There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels.
On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.
The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area.
The LPC47M172 is register compatible with SMSC’s proprietary 82077AA core.

Product Features
* 3.3V Operation (5V tolerant)
* LPC Interface
- Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
* ACPI 1.0b/2.0 Compliant
* Programmable Wake-up Event Interface
* PC99a/PC2001 Compliant
* General Purpose Input/Output Pins (13)
* Fan Tachometer Inputs (2)
* Green and Yellow Power LEDs
* ISA Plug-and-Play Compatible Register Set
* Motherboard GLUE Logic
- 5V Reference Generation
- 5V Standby Reference Generation
- IDE Reset/Buffered PCI Reset Outputs
- Power OK Signal Generation
- Power Sequencing
- Power Supply Turn On Circuitry
- Resume Reset Signal Generation
- Hard Drive Front Panel LED
- Voltage Translation for DDC to VGA Monitor
- SMBus Isolation Circuitry
- CNR Dynamic Down Control
* 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core
- Supports One Floppy Drive
- Configurable Open Drain/Push-Pull Output Drivers
- Supports Vertical Recording Format
* 16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
* Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
* 480 Address, Up to Eight IRQ and Three DMA Options
* Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates
- Programmable Precompensation Modes
* Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
* Serial Ports
- Two Full Function Serial Ports
- High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
* Infrared Port
- Multiprotocol Infrared Interface
- 32-Byte Data FIFO
- IrDA 1.0 Compliant
- 480 Address, Up to 15 IRQ and Three DMA Options
* Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Three DMA Options
* Interrupt Generating Registers
- Registers Generate IRQ1 – IRQ15 on Serial IRQ Interface.
* XOR-Chain Board Test
* 128 Pin MQFP Package, 3.2 mm Footprint


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Product Overview
 The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus.
Individually-erasable memory blocks are optimally sized for code and data storage.
Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map.
The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations at 3 V or 12 V VPP.
With the 3 V I/O option, VCC and VPP can be tied together for a simple, ultra-low-power design.
In addition to I/O voltage flexibility, the dedicated VPP input provides complete data protection when VPP ≤ VPPLK.
The device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable OTP data registers.
Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data.
Additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status.
A command User Interface(CUI) serves as the interface between the system processor and internal operation of the device.
A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode.
The device automatically enters APS mode following read cycle completion.
Standby mode begins when the system deselects the flash memory by deasserting CE#.
The deep power-down mode begins when RP# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings.
Combined, these three power-savings features significantly enhanced power consumption

Product Features
* Flexible SmartVoltage Technology
- 2.7 V – 3.6 V Read/Program/Erase
- 12 V for Fast Production Programming
* 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
- Reduces Overall System Power
* High Performance
- 2.7 V– 3.6 V: 70 ns Max Access Time
* Optimized Architecture for Code Plus Data Storage
- Eight 4 Kword Blocks, Top or Bottom Parameter Boot
- Up to One Hundred-Twenty-Seven 32 Kword Blocks
- Fast Program Suspend Capability
- Fast Erase Suspend Capability
* Flexible Block Locking
- Lock/Unlock Any Block
- Full Protection on Power-Up
- WP# Pin for Hardware Block Protection
* Low Power Consumption
- 9 mA Typical Read
- 7 A Typical Standby with Automatic Power Savings Feature (APS)
* Extended Temperature Operation
- 40 °C to +85 °C
* 128-bit Protection Register
- 64 bit Unique Device Identifier
- 64 bit User Programmable OTP Cells
* Extended Cycling Capability
- Minimum 100,000 Block Erase Cycles
* Software
- Intel® Flash Data Integrator (FDI)
- Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice)
- Intel Basic Command Set
- Common Flash Interface (CFI)
* Standard Surface Mount Packaging
- 48-Ball μBGA*/VFBGA
- 64-Ball Easy BGA Packages
- 48-Lead TSOP Package
* ETOX™VIII (0.13 μm) Flash Technology
-16, 32 Mbit
* ETOX™VII (0.18 μm) Flash Technology
- 16, 32, 64 Mbit
* ETOX™VI (0.25 μm) Flash Technology
- 8, 16 and 32 Mbit


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·  Extended system operating range due to powerful AM/PM demodulation technique
·  Ideally suited for "Intelligent Antenna" and "Active Antenna" architectures
·  High antenna drive capabilities, CW: 200mAp
·  Low antenna driver output resistance, 3.5 W
·  Excellent receiver sensitivity, 2mVpp
·  Large receiver dynamic range
·  Programmable clock divider, modulator, receiver gain and filter characteristics
·  Fast "read after write" receiver settling characteristics
·  On-chip receive EMI filter
·  Antenna failure mode detection
·  Few external components
·  Operating supply voltage: 4.5 to 5.5 V
·  Power down mode: 7mA @ 5.5 V
·  14-pin SO package

General Description
The PCF7991 is a highly integrated and powerful advanced basestation IC, ABIC, ideally suited for vehicle immobilisation applications. The device incorporates all necessary functions to facilitate reading and writing of transponders.
The ABIC, PCF7991 employs a unique AM/PM demodulation technique that extends the system operating range compared with simple envelope detection. Optimised to operate with the Philips transponder family (PCF79xx), the ABIC can be used in combination with commonly available transponder that employ ASK modulation. ASK modulation and receive characteristics are widely programmable for powerful system adaptation. The ABIC fits "Intelligent Antenna" as well
as "Active Antenna" applications.
The carrier frequency can be derived from an on-chip oscillator or an external clock source. A wide range of clock frequencies can be applied due to the programmable on-chip clock divider circuitry.
The device enables system diagnostic functions by antenna fail detection features.
Communication with the device and the transponder is provided via the serial microcontroller interface.
Employing CMOS technology, the device features low power operation and supports Idle and Powerdown modes.
TAG Advanced, ic

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The WM8741 is a very high performance stereo DAC designed for audio applications such as professional recording systems, A/V receivers and high specification CD, DVD and home theatre systems. The device supports PCM data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8741 also supports DSD bitstream data format, in both direct DSD and PCM-converted DSD modes.
The WM8741 includes fine resolution volume and soft mute control, digital de-emphasis and a range of advanced digital filter responses, followed by a digital interpolation filter, multi-bit sigma delta modulator and stereo DAC. Wolfson’s patented architecture optimises the linearity of the DAC and provides maximum insensitivity to clock jitter.
The digital filters include several selectable roll-off and performance characteristics. The user can select between standard sharp or slow roll-off responses. In addition, the WM8741 includes a selection of advanced digital filter characteristics including non-half band filters and minimum phase filters. This flexibility provides a range of benefits, such as significantly reduced pre-ringing and minimal group delay. The internal digital filters can also be by-passed and the WM8741 used with an external digital filter.
The WM8741 supports two connection schemes for audio DAC control. The 2/3 wire serial control interface provides access to all features. A range of features can also be accessed by hardware control interface.
The WM8741 is available in a convenient 28-SSOP package, and is pin compatible with the WM8740.

• Advanced Ultra High Performance Multi-bit Sigma-Delta Architecture
− 128dB SNR (‘A’-weighted mono @ 48kHz)
− 125dB SNR (‘A’-weighted stereo @ 48kHz)
− 123dB SNR (non-weighted stereo @ 48kHz)
− -100dB THD @ 48kHz
− Differential analogue voltage outputs
− High tolerance to clock jitter
• PCM Mode
− Sampling frequency: 32kHz to 192kHz
− Input data word length support: 16 to 32-bit
− Supports all standard audio interface formats
− Selectable advanced digital filter responses
− Includes linear/minimum phase and range of tailored characteristics
− Enables low pre-ringing, minimal latency
− Optional interface to industry standard external filters
− Digital volume control in 0.125dB steps with soft ramp and soft mute
− Anti-clipping mode to prevent distortion even with input signals recorded up to 0dB
− Selectable de-emphasis support
− Zero Flag output
• DSD Mode
− DSD bit-stream support for SACD applications
− Support for normal or phase modulated bit-streams
− Direct or PCM converted DSD paths (DSD Plus)
− DSD mute
• Hardware or software control modes:
− 2 and 3 wire serial control interface support
• Pin compatible with WM8740
• 4.5V to 5.5V analogue, 3.0V to 3.6V digital supply operation
• 28-lead SSOP Package

• Professional audio systems
• CD, DVD, SACD audio
• Home theatre systems
• A/V receivers


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- Multimedia System
- ATM Switches
- Routers
- Cable Modems
- Wireless Base Stations
- SONET(Synchronous Optical Network) Multiplexers
- TBC(Time Base Corrector)
- Hard Disk cache memory

The AL4CE2x1 series memory products are high-performance, low-power 9bit read/write FIFO (First-In-First-Out) memory chip designed to buffer high speed streaming data for a wide range of applications. The AL4CE2x1 FIFO memories are the advanced version of AL4CS2x1. Retransmit is supported in this product series to reduce designing efforts.

* High performance, low-power, FIFO(First- In First-Out) memory
* 512 x 9 bit I/O port (AL4CE211)
* 1K x 9 bit 1/O port (AL4CE221)
* 2K x 9 bit I/O port (AL4CE231)
* 4K x 9 bit I/O port (AL4CE241)
* 8K x 9 bit I/O port (AL4CE251)
* High clock speed (133MHz)
* Fully independent read/write access
* Retransmit the data (reread the data)
* Empty, Full, and programmable Almost Empty, Almost Full flags
* Output enable control (data skipping)
* 3.3V power with 5V signal tolerant input
* Standard 32-pin TQFP


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The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone.

Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media.

The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices
support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a
single 2.5 V power supply.

* Enterprise switches
* IP telephony switches
* Storage Area Networks
* Multi-port Network Interface Cards (NICs)

Product Features
* Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters.
* 100BASE-FX fiber-optic capability on all ports.
* 2.5 V operation.
* Low power consumption; 250 mW per port typical.
* Multiple RMII or SMII/SS-SMII ports for independent PHY port operation.
* Auto MDI/MDIX crossover capability.
* Proprietary Optimal Signal Processing™ architecture improves SNR by 3 dB over ideal analog filters.
* Optimized for dual-high stacked RJ-45 applications.
* MDIO sectionalization into 2x4 or 1x8 configurations.
* Supports both auto-negotiation systems and legacy systems without auto-negotiation
* Robust baseline wander correction.
* Configurable through the MDIO port or external control pins.
* JTAG boundary scan.
* 208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE.
* 241-ball BGA: LXT9785BC, LXT9785EBC.
* 196-ball BGA: LXT9785MBC
* DTE detection for remote powering applications (LXT9785E only).
* Extended temperature operation of -40oC to +85oC (LXT9785HE).

LXT9785HC, LXT9785EHC, LXT9785HE, LXT9785E

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