GENERAL DESCRIPTION
W9812G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. W9812G6IH delivers a data bandwidth of up to 200M words per second (-5). For different application, W9812G6IH is sorted into the following speed grades: -5/-6/-6C and -75. The –5 is compliant to the 200MHz/CL3 specification. The –6/-6C/-6I is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G6IH is ideal for main memory in high performance applications.

FEATURES
*3.3V ± 0.3V Power Supply
*Up to 200 MHz Clock Frequency
*2,097,152 Words × 4 banks × 16 bits organization
*Self Refresh Mode
*CAS Latency: 2 and 3
*Burst Length: 1, 2, 4, 8 and full page
*Burst Read, Single Writes Mode
*Byte Data Controlled by LDQM, UDQM
*Auto-precharge and Controlled Precharge
*4K Refresh cycles / 64 mS
*Interface: LVTTL
*Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant

W9812G6IH-5, W9812G6IH-6, W9812G6IH-6C, W9812G6IH-6I, W9812G6IH-75

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DISTINCTIVE CHARACTERISTICS
*Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port
*Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards
*84-pin PLCC and 100-pin PQFP Packages
*80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as
PCMCIA
*Modular architecture allows easy tuning to specific applications
*High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer
*Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency
and support the following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of collision frames
— Automatic retransmission with no FIFO reload
*Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs
*Direct FIFO read/write access for simple interface to DMA controllers or l/O processors
*Arbitrary byte alignment and little/big endian memory interface supported
*Internal/external loopback capabilities
*External Address Detection Interface (EADI) for external hardware address filtering in
bridge/router applications
*JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test
*Integrated Manchester Encoder/Decoder
*Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI)
*Supports the following types of network

interface:
— AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU
— DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU
— General Purpose Serial Interface (GPSI) to external encoding/decoding scheme
— Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port
*Sleep mode allows reduced power consumption for critical battery powered applications
*5 MHz-25 MHz system clock speed
*Support for operation in industrial temperature range (–40°C to +85°C) available in all three
packages

GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system
specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers.
The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE
device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system.


AM79C940
AM79C940

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