GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI encoding transmitter and CMI decoding receiver. The chip derives high speed timing and data signals for SONET/SDH or PDH-based equipment. The circuit is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figures 1a and 1b show typical network applications.
The S3031B has two independent VCOs which are synchronized to the local NRZ transmitted data and the received CMI data respectively. The chip can be used with either a 19.44 MHz or a 38.88 MHz reference clock when operated in the SONET/SDH OC-3 mode. In E4 mode the chip can be operated with a 17.408 MHz or a 34.816 MHz reference in support of existing system clocking schemes. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbps and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs and the PECL nibble clock interface guarantee compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3031B is packaged in a 0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components onchip for a coaxial cable interface, including analog transformer driver circuitry and equalization interface circuitry. Discrete controls permit separate selection of CMI or NRZ operation and analog (coaxial copper) or PECL (optical module) media interfaces. Both line loopback and diagnostic local loopback operation are supported.

FEATURES
*Complies with Bellcore and ITU-T specifications
*On-chip high-frequency PLLs for clock generation and clock recovery
*On-chip analog circuitry for transformer driver and equalization
*Supports 139.264 Mbps (E4) and 155.52 Mbps (OC-3) transmission rates
*Supports 139.264 Mbps and 155.52 Mbps Coded Mark Inversion (CMI) interfaces
*TTL Reference frequencies of 19.44 and 38.88 MHz (OC-3) or 17.408 and 34.816 MHz (E4)
*Interface to both PECL and TTL logic
*Lock detect on clock recovery function — monitors run length and frequency
*Serial and 4 bit (nibble) system interfaces
*Low jitter PECL interface
*+5V operation
*100 PQFP/TEP package
*Supports both electrical and optical interfaces

APPLICATIONS
*ATM over SONET/SDH
*OC-3/STM-1 or E4-based transmission systems
*OC-3/STM-1 or E4 modules
*OC-3/STM-1 or E4 test equipment
*Section repeaters
*Add Drop Multiplexers (ADM)
*Broadband cross-connects
*Fiber optic terminators
*Fiber optic test equipment

S3031BH0

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GENERAL DESCRIPTION
 The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment.
The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock.
The chip outputs a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
The phase detector compares the phase relationship between the VCO output and the serial data input.
A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.
A block diagram is shown in Figure 2.
There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.

FEATURES
* Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
* Five on-chip high frequency PLLs with internal loop filters for clock recovery
* Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
* Clock Multiplier PLL for transmit clock generation
* 19.44 or 51.84 MHz reference frequency
* Lock detect—monitors run length and frequency
* Low-jitter differential interface
* 3.3V supply
* Available in a 64-pin TQFP package
* Compatible with IgT WAC-413 ATM Quad- UNI processor

S3029A

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General Description
The MAX3963 is a low-noise transimpedance preamplifier for FDDI and 155Mbps ATM optical receivers. The MAX3963’s dynamic range is optimized for use in multimode LED-based applications.
The preamplifier converts a small photodiode current to a differential voltage, with typical transimpedance of 22kΩ. Input-referred noise of only 21nA allows detection of signals as small as 267nA, while pulse-width distortion is only 85ps with a 60μA input signal. In a 1300nm multimode receiver, with responsivity of 0.7A/W, the MAX3963’s dynamic range spans from
-36dBm to -13.7dBm. The circuit operates from a single +5V supply, and typically consumes only 60mW power.
The MAX3963 die includes a filter connection, which provides positive bias for the photodiode through a 1kΩ resistor to VCC. This feature, combined with the small die size, allows the MAX3963 to fit easily into a TO-style package with a photodiode.
The differential outputs are back terminated with 60Ω per side, allowing the easy use of filters to improve sensitivity.
The MAX3963 is designed to be used with the MAX3964 limiting amplifier IC. It is available in an 8-pin SO package and as dice.

Applications
* 21nA Total RMS Noise
* 22kΩ Differential Transimpedance
* 180MHz Bandwidth
* 60mW Typical Power Consumption
* 60μA Peak Input Current
*  Low, 85ps Pulse-Width Distortion

MAX3963CSA

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