General Description
The RT9645 is a combo regulator which is compliant to ACPI specification for desktop/server power management and system application. The part features one switching regulator for DDR memory VDDQ power; a second PWM controller for GMCH core power, a LDO controller for FSB_ VTT termination, a LDO controller for 5VSB to 3VSB conversion; and a dual power control 5VDL for S0 and S3 system power.
The part is generally operated to conform to ACPI specification. In S3 mode, only VDDQ and 3.3VSB regulators remain on while the FSB_ VTT regulator is off.
In the transition from S3 to S0, an internal SS capacitor is attached for linear regulators to control its slew rate respectively to avoid inrush current induced.
RT9645 supports both Intel VR11 and AMD K8 platform.
There is extra control pin VTT_EN to enable FSB_VTT regulator at AMD K8 mode. This part also implements PWM1 (VDDQ) enabled by release COMP1 at AMD K8 application. This part is assemblyed in the tiny VQFN-24L 4x4 package.

* Integrated 5 Channels Power Regulator
* DC/DC Buck PWM Regulator (Driver Included)
* DC/DC Buck PWM Controller
* Linear Regulator Controller for FSB_VTT Power
* 3.3VSB Linear Regulator Controller with 40mA Output Capability
* 5VDL Switch Control
* Conform to ACPI Specification, Supporting Power Management at S0, S3, and S5 State
* 300kHz Fixed Frequency Oscillator
* Low-Side RDS(ON) Current Sensing for Precision Over-Current Detection
* Thermal Shutdown
* Small 24-Lead VQFN Package
* RoHS Compliant and 100% Lead (Pb)-Free

* Desktop System Power
* Server System Power


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The CDP1020 is an ACPI compliant Device Bay Controller (DBC) that can control two device bays. The controller interfaces to the host system through the industry standard I2C or System Management Bus (SMBus) and is fully compliant with Device Bay Specification 0.90. The CDP1020 is designed to be compatible with the integrated SMBus host controller of the PiiX4/PiiX6 in Intel Architecture platforms. The CDP1020 is designed to be placed on the host motherboard, on a riser, or adjacent to the Device Bay connectors. The required clock source is generated from an internal oscillator on the CLK pin, with an external RC to set the frequency. This lowers the system cost and allows the CDP1020 to remain active during S3-S5 system states where all clock generators have been stopped. One of the key features of this device is the on-chip level shifters that provide slew rate controlled, direct gate drive for external N-Channel MOSFETs (Intersil HUF76113DK8 recommended) to switch the device bay VID supplies. Switching an N-Channel device as opposed to a P-Channel reduces both device cost and device count, resulting in an overall lower system cost. Configuration data for the CDP1020, including subsystem vendor ID, subsystem revision, bay size and device bay capabilities are designed to be written into the CDP1020 by the system BIOS at power up. The registers for this data are write-once-only and thus become read-only after the initial BIOS write. The address selection pins (AD1 and AD0) allow the CDP1020 to occupy any one of four I2C/SMBus addresses. This enables up to four CDP1020 devices to coexist in a system. The CDP1020 implements high current outputs for direct drive (with a limiting resistor) of the optional bay status LEDs. These indicators are two color (green/amber) common anode or anti-parallel LEDs that indicate the device bay status per the Device Bay Specification 0.90.

• Fully Compliant with Device Bay Specification 0.90 and ACPI Specification 1.0
• Industry Standard SMBus/I2C Interface
• Controls for Two Device Bays
• Onboard Level Shifting for Direct Drive of N-Channel MOSFET VID Switches
• Integrated Pull-up Resistors on 1394PRx, USBPRx, SECUREx, and REMREQx Inputs
• RC Type Oscillator - Low Cost and Low Power Consumption
• Operational Voltage from 3.3 to 5.5V
• “5V Tolerant” Inputs at all Operating Voltages
• Write-Once BIOS/External Configuration
• Removal Request Input for Each Bay
• Security Lock Input for Each Bay
• High Current Device Bay LED Indicator Drivers With Separate High-Side Power Input
• Configurable Level/Pulse Bay Solenoid Drivers
• Programmable Insertion Time Out Delay
• HCMOS Technology; 28 Lead Plastic SOIC

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