Description
The EM44AM1684LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

Features
*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBA-5F, EM44AM1684LBA-37F, EM44AM1684LBA-3F

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General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Features
*PC100- and PC133-compliant
*Fully synchronous; all signals registered on positive edge of system clock
*Internal pipelined operation; column address can be changed every clock cycle
*Internal banks for hiding row access/precharge
*Programmable burst lengths: 1, 2, 4, 8, or full page
*Auto precharge, includes concurrent auto precharge, and auto refresh modes
*Self refresh mode
*64ms, 8,192-cycle refresh
*LVTTL-compatible inputs and outputs
*Single +3.3V ±0.3V power supply

MT48LC32M8A2, MT48LC16M16A2

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