Functional Description
The architecture of the XC236x combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external resources (see Figure 3). This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC236x.
The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC236x.

Summary of Features
For a quick overview or reference, the XC236x’s properties are listed here in a condensed way.
*High Performance 16-bit CPU with 5-Stage Pipeline
– 15 ns Instruction Cycle Time at 66 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle 32-bit Addition and Subtraction with 40-bit result
– 1-Cycle Multiplication (16 × 16 bit)
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Background Division (32 / 16 bit) in 21 Cycles
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
*16-Priority-Level Interrupt System with up to 79 Sources, Selectable External Inputs for Interrupt Generation and Wake-Up, Sample-Rate down to 15 ns
*8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
*Clock Generation from Internal or External Clock Sources, via on-chip PLL or via Prescaler
*On-Chip Memory Modules
– 1 Kbyte On-Chip Stand-By RAM (SBRAM)
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 16 Kbytes On-Chip Data SRAM (DSRAM)
– Up to 32 Kbytes On-Chip Program/Data SRAM (PSRAM)
– Up to 576 Kbytes On-Chip Program Memory (Flash Memory)
*On-Chip Peripheral Modules
– Two Synchronizable A/D Converters with a total of 16 Channels, 10-bit Resolution, Conversion Time down to 1.2 μs, Optional Data Preprocessing (Data Reduction, Range Check)
– 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Two Capture/Compare Units for flexible PWM Signal Generation (CCU6x)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Six Serial Interface Channels to be used as UART, LIN, High-Speed Synchronous Channel (SPI/QSPI), IIC Bus Interface (10-bit addressing, 400 kbit/s), IIS Interface
– On-Chip MultiCAN Interface (Rev. 2.0B active) with 64 Message Objects (Full CAN/Basic CAN) on 3 CAN Nodes and Gateway Functionality
– On-Chip Real Time Clock
*Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Four Programmable Chip-Select Signals
*Single Power Supply from 3.0 V to 5.5 V
*Programmable Watchdog Timer and Oscillator Watchdog
*Up to 75 General Purpose I/O Lines
*On-Chip Bootstrap Loader
*Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
*On-Chip Debug Support via JTAG Interface
*100-Pin Green LQFP Package, 0.5 mm (19.7 mil) pitch


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