The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD power supply.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with ECC on). The device also has hardware security features; a write protect pin is available to give hardware protection against Program and Erase operations.
The devices feature an open-drain, ready/busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable “Don’t Care” feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the Read operation.
There is the option of a unique identifier (serial number), which allows the NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm) packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the category of second level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label.
The devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.

*High density multilevel cell (MLC) Flash memory
-Up to 16 Gbit memory array
-Up to 512 Mbit spare area
-Cost-effective solutions for mass storage applications
*NAND interface
-x 8 bus width
-Multiplexed address/data
*Supply voltage: VDD = 2.7 to 3.6 V
*Page size: (2048 + 64 spare) bytes
*Block size: (256K + 8K spare) bytes
*Multiplane architecture
-Array split into two independent planes
-Program/erase operations can be performed on both planes at the same time
*Page read/program
-Random access: 60 μs (max)
-Sequential access: 25 ns (min)
-Page program operation time: 800 μs (typ)
*Multipage program time (2 pages): 800 μs (typ)
*Fast block erase
-Block erase time: 2.5 ms (typ)
*Multiblock erase time (2 blocks): 2.5 ms (typ)
*Status register
*Electronic signature
*Serial number option
*Chip enable ‘don’t care’
*Data protection
-Hardware program/erase locked during power transitions
*Development tools
-Error correction code models
-Bad block management and wear leveling algorithm
-HW simulation models
*Data integrity
-10,000 program/erase cycles (with ECC)
-10 years data retention
*ECOPACK® packages available


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