DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. The device is offered in a 48-pin TSOP (1) and 63-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE) and output enable (OE) controls.
The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This invokes the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.
A sector is Typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed, the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

FEATURES
*0.23 μm Process Technology
*Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
*Compatible with JEDEC-standard Commands
- Use the same software commands as E2PROMs
*Compatible with JEDEC-standard Worldwide Pinouts
- 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
*Minimum 100,000 Program/Erase Cycles
*High Performance
- 80 ns maximum access time
*Sector Erase Architecture
- Eight 4 K word and sixty-three 32 K word sectors in word mode
- Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
- Any combination of sectors can be concurrently erased. Also supports full chip erase.
*Boot Code Sector Architecture
- T = Top sector
- B = Bottom sector
*HiddenROM Region
- 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
- Factory serialized and protected to provide a secure electronic serial number (ESN)
*WP/ACC Input Pin
- At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
- At VACC, increases program performance
*Embedded EraseTM* Algorithms
- Automatically pre-programs and erases the chip or any sector
*Embedded ProgramTM* Algorithms
- Automatically writes and verifies data at specified address
*Data Polling and Toggle Bit feature for detection of program or erase cycle completion
*Ready/Busy output (RY/BY)
- Hardware method for detection of program or erase cycle completion
*Automatic sleep mode
- When addresses remain stable, automatically switch themselves to low power mode.
*Low VCC write inhibit ≤ 2.5 V
*Erase Suspend/Resume
- Suspends the erase operation to allow a read data and/or program in another sector within the same device
*Sector group protection
- Hardware method disables any combination of sector groups from program or erase operations
*Sector Group Protection Set function by Extended sector group protection command
*Fast Programming Function by Extended Command
*Temporary sector group unprotection
- Temporary sector group unprotection via the RESET pin.
*In accordance with CFI (Common Flash Memory Interface)
#*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

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