The M830 Series CDR module is specifically designed to regenerate the spectral clock component from an incoming NRZ data stream, incorporating forward error correction, and output a low-jitter clock and retimed complementary data.
The module utilizes a phase-locked loop architecture incorporating a high-stability, low noise SAW VCO to provide extremely low jitter clock and data outputs. The incoming data is frequency doubled to recover the clock component. The clock signal is then filtered by a microwave band pass filter to remove wide band noise and spurious signal. This signal is further filtered using the narrow band SAW VCO based PLL to minimize the noise close to the carrier. The low jitter clock is then used to retime the data and serves as the module’s clock output. The module provides usercontrolled clock phase shifter and output data crossover adjustments to optimize system performance.
PLL lock-in range and loop transfer characteristics are optimized for minimal jitter in accordance with ITU and Bellcore standards for SONET/SDH systems.

*Superior PLL-based jitter performance
*8psec p-p jitter
*0.9Vp-p complementary data outputs
*1 Ul externally adjustable clock phase
*200mVp-p input sensitivity
*Optional adjustable bias @ data input to decision circuit
*Externally adjustable decision threshold

*SONET OC-192 and SDH STM Physical
*Layer and Clock and Data Recovery
*Applications Incorporating Forward
*Error Correction


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