Product Description
 The LE28F1101T is a 64K ×16 CMOS sector erase, word program EEPROM.
The LE28F1101T is manufactured using SANYO's proprietary, high performance CMOS Flash
EEPROM technology.
Breakthroughs in EEPROM cell design and process architecture attain better reliability and
manufacturability compared with conventional approaches.
The LE28F1101T erases and programs with a 5-volt only power supply.
LE28F1101T is offered in TSOP40 (10×14mm) packages.
Featuring high performance programming, LE28F1101 typically word programs in 30μs.
The LE28F1101 typically sector (128word) erases in 2ms.
Both program and erase times can be optimized using interface feature such as Toggle
bit or DATA Polling to indicate the completion of the write cycle.
To protect against an inadvertent write, the LE28F1101T has on chip hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of applications, the LE28F1101T is offered with a guaranteed sector write endurance of 104 cycles.
Data retention is rated greater than 10 years.
The LE28F1101T is best suited for applications that require reprogrammable nonvolatile mass storage of program or data memory.
For all system applications, the LE28F1101T significantly improves performance and reliability,
while lowering power consumption when compared with floppy diskettes or EPROM approaches.
EEPROM technology makes possible convenient and economical updating of codes and control programs on-line.
The LE28F1101T improves flexibility, while lowering the cost, of program and configuration storage applications.
Figure 1 shows the pin assignments for the 40 lead Plastic TSOP packages.
Figure 2 shows the functional block diagram of the LE28F1101T.
Pin description and operation modes can be found in Tables 1 through 3.

Device Operation
Commands are used to initiate the memory operation functions of the device.
Commands are written to the device using standard microprocessor write sequences.
A command is written by asserting WE low while keeping CE low.
The address bus is latched on the falling edge of WE, CE , whichever occurs last.
The data bus is latched on the rising edge of WE, CE , whichever occurs first. However, during
the software write protection sequence the addresses are latched on the rising edge of OE or CE , whichever occurs first.

* CMOS Flash EEPROM Technology
* Single 5-Volt Read and Write Operations
* Sector Erase Capability: 128word per sector
* Fast Access Time: 40ns/45ns/55ns/70ns
* Low Power Consumption
- Active Current (Read): 50 mA (Max.)
- Standby Current: 100 μA (Max.)
* High Read/Write Reliability
- Sector-write Endurance Cycles: 104
- 10 Years Data Retention
* Latched Address and Data
* Self-timed Erase and Programming
* Word Programming: 40μs (Max.)
* End of Write Detection: Toggle Bit/ DATA Polling
* Hardware/Software Data Protection
* Packages Available
- LE28F1101T : 40-pin TSOP Normal(10×14mm)


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