Description
The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between all of these elements.
The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port.
The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems.
A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options.
The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB).
The GLBs are labeled A0, A1...B7 (Figure 1).
There are a total of 16 GLBs in the ispLSI 1016EA device.
Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and a dedicated input.
All of the GLB outputs are brought back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Features
* HIGH-DENSITY PROGRAMMABLE LOGIC
- 2000 PLD Gates
- 32 I/O Pins, One Dedicated Input
- 96 Registers
- High-Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Functionally Compatible with ispLSI 1016E
* NEW FEATURES
- 100% IEEE 1149.1 Boundary Scan Testable
- ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
- User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin)
- Open-Drain Output Option
* HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 200 MHz Maximum Operating Frequency
- tpd = 4.5 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
- 100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
- Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
- Reprogram Soldered Device for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue Logic and Structured Designs
- Enhanced Pin Locking Capability
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Programmable Output Slew Rate Control to Minimize Switching Noise
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global Interconnectivity

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