DESCRIPTION
The HY62U8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62U8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V.
FEATURES
*Fully static operation and Tri-state outputs
*TTL compatible inputs and outputs
*Low power consumption
*Battery backup(LL-part)
-2.0V(min) data retention
*Standard pin configuration
-32pin 525mil SOP
-32pin 400mil TSOP-II (Standard and Reversed)
HY62U8400A, HY62U8400A-E, HY62U8400A-I
The HY62U8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62U8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V.
FEATURES
*Fully static operation and Tri-state outputs
*TTL compatible inputs and outputs
*Low power consumption
*Battery backup(LL-part)
-2.0V(min) data retention
*Standard pin configuration
-32pin 525mil SOP
-32pin 400mil TSOP-II (Standard and Reversed)
HY62U8400A, HY62U8400A-E, HY62U8400A-I
