Specifications
• Density: 512M bits
• Organization
 32M words × 4 bits × 4 banks (EDE5104AJSE)
 16M words × 8 bits × 4 banks (EDE5108AJSE)
 8M words × 16 bits × 4 banks (EDE5116AJSE)
• Package
 60-ball FBGA (EDE5104/08AJSE)
 84-ball FBGA (EDE5116AJSE)
 Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• 1KB page size
 Row address: A0 to A13
 Column address: A0 to A9, A11 (EDE5104AJSE) A0 to A9 (EDE5108AJSE)
• 2KB page size (EDE5116AJSE)
 Row address: A0 to A12
 Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
 Sequential (4, 8)
 Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
 Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
 TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation

EDE5108AJSE
EDE5116AJSE
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