Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively.
Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock.
Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations.
This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved).
Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation.
This feature enables flexible performance optimization for a variety of applications.

*PC100/133 compliant
-2,097,152 words × 8 bits × 4 banks (8M×8)
-1,048,576 words × 16 bits × 4 banks (4M×16)
*Fully synchronous
-All signals referenced to positive edge of clock
*Four internal banks controlled by BA0/BA1 (bank select)
*High speed
-133/125/100 MHz
-5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
*Low power consumption
-Standby: 7.2 mW max, CMOS I/O
*4096 refresh cycles, 64 ms refresh interval
*Auto refresh and self refresh
*Automatic and direct precharge
*Burst read, single write operation
*Can assert random column address in every cycle
*LVTTL compatible I/O
*3.3V power supply
*JEDEC standard package, pinout and function
-400 mil, 54-pin TSOP II
*Read/write data masking
*Programmable burst length (1/2/4/8/full page)
*Programmable burst sequence (sequential/interleaved)
*Programmable CAS latency (2/3)


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