· Maximum Sample Rate: 125 MSPS
· 14-Bit Resolution with No Missing Codes
· 3.5 dB Coarse Gain and up to 6 dB TPrraodgera-Omfmf able Fine Gain for SNR/SFDR
· Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
· Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400
· Clock Duty Cycle Stabilizer
· Internal Reference with Support for External Reference
· No External Decoupling Required for References
· Programmable Output Clock Position and Drive Strength to Ease Data Capture
· 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
· 32-QFN Package (5 mm ´ 5 mm)
· Pin Compatible 12-Bit Family (ADS612X)

· Wireless Communications Infrastructure
· Software Defined Radio
· Power Amplifier Linearization
· 802.16d/e
· Test and Measurement Instrumentation
· High Definition Video
· Medical Imaging


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