New products boost vibration resistance by 50 percent^*2

Tokyo -- Toshiba Corporation today announced the latest additions to its market-leading lineup of 2.5-inch hard disk drives (HDD) for automotive applications: an 80GB drive offering the industry's largest^*1capacity, and a 40GB drive. The drives will be used in such applications as car navigation systems, and will be released in industrial and retail versions. Sample shipping of the drives has started and mass production will start in March 2008.

Toshiba's automotive HDD have earned an unrivaled reputation for environmental toughness and performance, and made the company the leader in the world automotive HDD market. With its latest drives, the company has further enhanced durability and increased data capacity, using perpendicular magnetic recording (PMR) to boost areal recording density and to raise storage capacity to 80GB (MK8050GAC and MK8050GACE), double that of Toshiba's current automotive drives^*2 .

Alongside higher storage, the drives offer numerous enhancements. Lighter moving parts, a highly rigid enclosure, and the vibration resistance achieved by a highly accurate head positioning system, takes overall, vibration resistance to 29.4m/s² (5-50Hz), a full 50% improvement over current automotive models^*2. In addition, an advanced aerodynamic design for the head slider, which “floats" the head on a cushion of air, maintains the flying head at a constant distance from the disk, a refinement that brings greater reliability to data read and write in low pressure conditions at high altitude. As a result, the new drives can operate at up to 5,500m above sea level, 1,200m higher than current automotive models^*2.

In addition to map data information for car navigation, the new HDD can be used in on-board entertainment systems, to store high capacity movie, digital image and music files.

Toshiba introduced its first HDD for automotive application in 2001. The company's highly durable and reliable products today command a share of approximately 85% of the global automotive HDD market^*3, and cumulative shipments now stand at over 7-million units.

The new drives are fully compliant with the EU RoHS directive.

Outline of New Models

Background

The integration of HDD with fast access speeds into car navigation systems is increasing, especially in Japan, due to usability; fast screen refresh and the ability to store such data as music and visual content. The same trend is now being seen overseas, including Europe, and HDD-based car navigation is expected to see global demand growth. Recently, alongside map data, the need to store entertainment data for the enjoyment of rear seat passengers is increasing, stimulating demand for higher capacity HDD.

In this situation, Toshiba is meeting market needs with the industry's largest^*180GB HDD for automotive application.

Key Features of New Products

Main Specifications

World's First Operational Semiconductor-Based Weather Radar Goes into Operation at Nagoya University

TOKYO -- Toshiba Corporation today announced that it has developed and delivered the world's first operational weather radar system that replaces electron tubes in the transmitter with a high-power semiconductor module. The new radar is only one sixth the size of conventional equipment but offers comparable output power, along with improved waveband efficiency and enhanced features. The first unit of the new system has been installed at the Hydrospheric Atmospheric Research Center at Nagoya University, Japan. The Nagoya radar operates in the 9GHz frequency band (X-band) and is the first solid-state weather radar to go into practical operation.

While the new weather radar is much more compact and offers much higher performance than conventional systems, it maintains the same level of output power by adopting a combination of gallium nitride (GaN) power field effect transistors (FET) and pulse compression technology, which strengthens peak output power. Implementation of fully digital data processing suppresses the spurious level, allowing the frequency separation required for interference suppression to be shortened to one fourth. This contributes to efficient use of crowded radio frequencies.

The new radar reinforces performance by adding innovative features: dual polarization observation enhances the precision of rainfall estimation by capturing the shape and size of raindrops and cloud; clear-air turbulence observation detects very low levels of signal scattering, enabling to observe air conditions including wind speed even in clear weather -- a very difficult task for most weather radars.

The new system has a modular structure for the antenna, transmitter and received signal processor, which supports more flexible physical system layout depending on the installation site and operation. As the new radar does not use electron tubes, which have to be periodically replaced and disposed of, it reduces environmental loads, meeting Toshiba's goal of maximizing the eco-efficiency of its products and systems.

Because of the limitation of bandwidth availability with increasing use of radio wave frequency resources, steady demand for solid-state radars is expected, as they can contribute to more efficient use of frequencies. Toshiba will market the new high-power semiconductor-based weather radar in both 9GHz band (X-band) and 5GHz band (C-band) versions, both in Japan and overseas, including sales of individual modules that build the system.

Product Outline

World's first perpendicular magnetic anisotropy MTJ device

Tokyo--Toshiba Corporation today announced important breakthroughs in key technologies for magnetoresistive random access memory (MRAM), a promising, next-generation semiconductor memory device. The company has successfully fabricated a MRAM memory cell integrating the new technologies and verified its stable performance. Full details of the new technologies were presented today at the 52^nd Magnetism and Magnetic Materials Conference in Tampa, Florida, USA which is being held from November 5^th to 9^th.

MRAM is a highly anticipated next-generation non-volatile semiconductor memory device that offers fast random write/access speeds, enhances endurance in operation with very low power consumption. MRAM can theoretically achieve high level integration as the memory cell structure is relatively simple.
In making these major advances, Toshiba applied and proved the spin transfer switching and perpendicular magnetic anisotropy (PMA) technologies in a magnetic tunnel junction, which is a key component in the memory cell.

Spin transfer switching uses the properties of electron spin to invert magnetization and writes data at very low power levels. It is widely regarded as a major candidate among next-generation principles for new memory devices. PMA aligns magnetization in the magnetic layer perpendicularly, either upward or downward, rather than horizontally as in in-plane shape anisotropy layers. The technology is being increasingly used to enhance for storage capacity for high-density hard disc drives (HDDs), and Toshiba has successfully applied it to a semiconductor memory device. With PMA data write operation and magnetic switching can be achieved at a low energy level. Toshiba also overcame the hurdle of achieving the required precision in the interface process and significantly cutting write power consumption.

In order to realize a miniature memory cell based on PMA, Toshiba optimized the materials and device structure of the new MRAM. Close observation of performance confirms stable operation (see the diagram for full explanation of structure).

Toshiba will further enhance development toward establishing fundamental technologies within the coming years.

Development of the new MRAM technologies was partly supported by grants from Japan's New Energy and Industrial Technology Development Organization (NEDO).

Outline of Development

(1) Cell Structure

A material with perpendicular magnetic anisotropy, which is used for recording media and a type of cobalt-iron, is employed in the magnetic layer, with magnesium oxide in the insulating layer and cobalt-iron-boron in the interface layers.

(2) Operational Results

Figure 1
	Resistance versus voltage pulses: Shows device resistance characteristics after voltage pulses are applied to perform write operation. The switching between high and low resistive states is clearly seen at the voltage threshold in both the positive and negative directions.
Figure 2
	Resistance versus DC magnetic field: Device resistance characteristics when the magnetic field is applied perpendicular to layers. The high and low resistive states are clearly observed, and are produced by the magnetization direction in the free layer with reference to the reference layer.

(3) Major characteristics and specifications of MRAM device

Achievement of 65.4W Output Power at 14.5GHz

TOKYO--Toshiba Corporation today announced that it has developed a gallium nitride (GaN) power field effect transistor (FET) for the Ku-band (12GHz to 18GHz) frequency range that achieves an output power of 65.4W at 14.5GHz, the highest level of performance yet reported at this frequency band. The main application of the new transistor will be in base stations for satellite microwave communications, which carry high-capacity signals, including high-definition broadcasts. Toshiba plans to start sample shipment of the new power FET by the end of 2007 and to go into mass production by the end of March 2008.

Advances in Ku-band microwave amplifiers focus on replacing the electron tubes conventionally used at this bandwidth with semiconductors, particularly GaN devices, which offer advantageous high power characteristics at higher microwave frequencies.

The new power FET has a high electron mobility transistor (HEMT) structure that Toshiba has optimized for the Ku-band. The company replaced source wire bonding with via hole technology^*1 to reduce parasitic inductance, and also improved overall design of the matching circuit for practical application at Ku-band frequencies.

Demand for GaN power FET for radars and satellite microwave communications base stations is growing steadily, both for new equipment and replacement of electron tubes. Toshiba will meet this demand with early commercialization of its new Ku-band power FET.

Full details of the new GaN power FET will be presented at the European Microwave Conference 2007, in Munich, Germany from October 8 to 12.

Background and development aims

Ever increasing communications flows in satellite microwave communications are driving demand for higher output power in signal amplifying devices, as is development of more powerful radar systems. Demand is particularly strong for GaN devices, which offer advantages over conventional gallium arsenide devices in heat dissipation and high power performance characteristics at high frequency.

Toshiba has taken the lead in applying GaN technology to power FET for microwave frequency applications. The company directed its initial efforts to the development and marketing of power FET for the 6GHz band (2005) and 9.5GHz (2006) band, and developed devices that achieved the worlds highest output power at those frequencies. The company has now extended its line-up to 14.5GHz. Toshiba will continue development for the18GHz to 30GHz frequencies (Ka-band) and beyond.

Outline of development

1. Device technology
Toshiba achieved the outstanding performance of the new FET by optimizing the composition and thickness of the AlGaN and GaN layers formed on the highly heat-conductive silicon carbide (SiC) substrate of the HEMT structure. To assure high performance at Ku-band frequencies, Toshiba has applied a shorter gate length of below 0.3 microns, and optimized the shape of each electrode and element configuration to enhance heat dissipation.

2. Process technology
To reduce the parasitic inductance and improve higher frequency performance, Toshiba developed a unique technology for forming via holes, which pass from the surface source electrode through the chip to the ground. Success in forming via holes in SiC substrate, recognized as a highly demanding process, is a breakthrough in development of the new FET.

As gate lengths shorten, suppression of current leakage at the gate electrode is essential for achieving high level performance. A unique overcoat process applied around each gate electrode contributes to suppressing gate leakage to 1/30 that of Toshiba's conventional approaches. Electron beam exposure technology is applied in order to secure stable processing of gate lengths below 0.3 micron meters.

Key characteristics

Starting mass production of world's first CSCM
ultra small camera module applying TCV technology

TOKYO--Toshiba Corporation today announced that it will reinforce its competitiveness in the CMOS image sensor business by bringing in-house the currently outsourced production of CMOS camera modules. Mass production of new products will start at Iwate Toshiba Electronics, a Toshiba Group company, from January 2008. Manufacturing will start with the latest addition to Toshiba's Dynastron™ ^*1 series of CMOS image sensors, an ultra small CSCM (chip scale camera module) that will be the first camera module manufactured with TCV (Through Chip Via) technology. The modules will be demonstrated at CEATEC JAPAN 2007 from October 2^nd, at Makuhari Messe, at Toshiba's booth, at 8C12.

As mobile consumer products with cameras, particularly mobile phones, become increasingly compact, demand is growing for ultra small CMOS camera modules with high image quality.

"In order to meet demand, we will refine our business model by bringing our manufacturing of CMOS camera modules into the Group," said Yoshio Ooida, the executive vice president of Toshiba's Semiconductor Company. "We plan to gradually increase the in-house manufacturing ratio of CSCM products. Integrating manufacturing of image sensors at Oita Operations with camera module at Iwate Toshiba Electronics will allow us to reinforce cost-competitiveness in CMOS image sensor business and to put in place optimized supply chain management. We will also further develop the business by increasing sensor manufacturing capacity at Oita Operations."

The new CSCM micro-camera modules will be the first produced with TCV technology, which reduces wire bonding a substrate area by mounting components directly on the wafer and running electrodes through the vias on the circuit board, securing them with balls of solders on the substrate. The new product also reduces pixel size, contributing to a module size up to 64%^*2 smaller than camera modules manufactured with the same sensors.

The application of balls of solder and heat resistant lenses that are not affected by reflow^*3 significantly reduces the process for camera mounting to the circuit boards of mobile consumer products manufacturers.

Image of CMOS camera modules

Outline of products

Specifications

Generation random number at 2Mbit per second with small circuit only 1200 square micrometers in area

TOKYO-- Toshiba Corporation today announced the development of a major advance in information security technology: A physical random-number generation circuit that achieves the world's highest output by area, and that generates random numbers at a data rate of 2.0 megabits a second. The newly developed random-number generator (RNG) has a circuit size of only 1,200 square micrometers but achieves the level of performance and reliability essential for integration into IC cards and mobile equipment.

The details of the technology were introduced on February 6, in Session 22.8 of IEEE International Solid-State Circuits Conference (ISSCC) 2008 in San Francisco.

The new RNG technology adopts a compact analogue/digital (A/D) converter which effectively amplifies analog noise signals and converts them to digital random numbers. The technology also integrates a Toshiba-developed compact noise source device. This generates the noise signal by using stochastic physical phenomenon of electrons trapped in the silicon nitride (SiN) layer of a transistor; the layer traps and releases high density electrons at a high generation rate.

Toshiba also confirmed that the new RNG circuit is not subject to temperature dependence, a long-standing reliability issue for physical RNG.

Hacker-proof encryption is essential for secure information transfers in financial transactions and personal information exchanges. Many encryption algorithms rely on high quality RNG that eliminate periodicity in generated numbers. Existing cryptographic security technology for IC cards is based on pseudo-RNG algorithms, which is nearing its limitations as network technology advances.

Toshiba will continue further development and improvement of the circuit, toward the practical use of the unpredictable, highly safe physical RNG in a few years.

Note: This work is supported in part by the National Institute of Information and Communications Technology (NICT) of Japan.

Outline of Development

Toshiba's new physical RNG circuit relies on a nanometer-scale noise source device that is not affected by temperature. This device generates large noise signals at high frequency. The newly developed circuit effectively digitizes these large, high frequency signals.

1. Filter and differential amplifier type A/D converter:
In its previous work on development of a compact RNG circuit, Toshiba employed a multi-vibrator circuit, where the noise source device was connected to the digitizer circuit in series. As a result, there was a trade-off between the magnitude of the noise and the generation rate; in order to increase the magnitude of the noise, resistance of the noise source device needs to be high, but this leads to a reduction in the circuit's generation rate.

The new technology employs a filter and differential amplifier with a comparator, which is separated from the noise source device. It can selectively extract the high frequency noise signals generated by the new device and achieve a random number generation rate approximately seven times higher than the multi-vibrator circuit: the increases performance to a practical level of 2.0Mb/s, against 0.3Mb/s with the earlier technology.

2. Downsized A/D converter:
The improved circuit downsizes the A/D converter. In general, there is a trade-off in RNG: the smaller the noise source device, the larger the circuit area. The high frequency noise signals generated by the noise source device allow Toshiba to reduce the size of the A/D converter, and to reduce entire RNG circuit area to 1,200 square micrometers, including the noise source device. This is 86.6% smaller than the next smallest physical RNG circuit yet announced, a breakthrough that realizes the world's highest performance in random number generation rate per area.

3. No temperature dependence:
Experimental tests in a range from -50 to 100° centigrade have confirmed the high-quality randomness of the numbers generated. Results show that the generated numbers are not affected by temperature, verifying the possibility of stable generation of random numbers under the temperature conditions in which IC cards and mobile equipment are used.

To Ship 16-Gigabit and 32-Gigabit Single-chip, Fabricated with Cutting-edge Process Technology Co-developed with SanDisk

TOKYO--Toshiba Corporation, reinforcing its leadership in the development and fabrication of powerful, high density NAND flash memory, today announced development of technology for a 16-gigabit (Gb) NAND flash memory chip fabricated with 43-nanometer (nm) process technology co-developed with SanDisk Corporation of Milpitas, California. The technology of the new chip was reported on February 6, in Session 23.6 of the International Solid-State Circuits Conference (ISSCC) 2008 in San Francisco.

The new 16Gb products have a chip area of approximately 120 square millimeters, about 30 percent less than the same-density NAND flash memories jointly developed by Toshiba and SanDisk and fabricated with 56nm process technology. Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56nm devices, with a dummy word-line cell at either end to prevent program disturbance. This technology contributes to reduce the number of select gates and to improve memory area efficiency. Modification of the peripheral circuit design also contributes to reduced chip area: the addition of high voltage switches to the circuit reduces the number of control-gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.

Toshiba will start shipments of commercial samples of new 16Gb (2 gigabyte) single-chip, multi-level cell (MLC) NAND flash memories, the current mainstream density, from today and start mass production from March. Toshiba intends to start mass production of 32Gb (4 gigabyte) NAND flash memories early in the third quarter of this year (July–September 2008). The new chips will be produced at Fab 4, the latest 300mm wafer fabrication facility at Toshiba's Yokkaichi Operations, in Mie prefecture, Japan.

By combining advanced process and MLC technologies, and through continued advances in production efficiency, Toshiba intends to enhance cost competitiveness and meet the needs of the NAND flash memory market.

TOKYO-- Toshiba Corporation today announced that it has realized the world's fastest circuit technology for embedded DRAM for System LSI, achieving a speed of 833MHz at 32Mb density. The technology will be applied to graphic processing LSI. The technology was today introduced at the ISSCC (International Solid State Circuits Conference), held at San Francisco CA from February 3^rd.

Embedded DRAM are applied to systems on chips for graphic application, as they can read larger data amounts at higher speeds than external memory. As video images achieve higher levels of definition, higher processing speeds of larger densities are required.

To realize high speed operation, Toshiba applied a "pseudo two port system," a technology that virtually divides the overall memory into two and then reads and writes data in parallel and alternately. By replacing conventional serial read and write system with the new parallel technology, and optimizing such circuits as the command structure, Toshiba achieved the world's highest level of embedded DRAM performance ad 32Mb, a density actually applicable to products.

System LSI with embedded DRAM memory will find application in next generation high-end digital consumer products, game applications, mobile phones, projectors and other image-related applications that require high speed transfer of large volumes of data. Toshiba plans to apply this technology to its leading edge 65nm system LSI process, and to meet market demand for advanced graphic applications through the early launch of SoC integrating the new embedded DRAM.

New agreement broadens and extends ongoing collaboration to include 32nm CMOS process technology

EAST FISHKILL, N.Y., TOKYO--December 18, 2007-- IBM and Toshiba Corporation today announced that they have entered into a joint development agreement on 32nm bulk complementary metal oxide semiconductor (CMOS) process technology.

Since December 2005, IBM and Toshiba have collaborated on fundamental advanced research related to semiconductor process technologies at the 32nm technology generation and beyond at the research facilities in Yorktown and Albany, New York. Building on the success of this ongoing research collaboration, the two companies have agreed to extend the scope of the joint development work to now include 32nm bulk CMOS process technology.

Under the new agreement, Toshiba joins a six company IBM Alliance for 32nm bulk CMOS process technology development * based in East Fishkill, New York.

Through this collaboration IBM and Toshiba plan to accelerate development of next-generation technology to achieve high-performance, energy-efficient chips at the 32nm process level, and to enhance the companies' leadership in the global semiconductor industry.

"This agreement caps a year of extraordinary momentum for IBM and its semiconductor Alliance Partners," said Gary Patton, vice president for IBM's Semiconductor Research and Development Center. "In 2008 we'll continue to strive to collectively deliver the industry breakthroughs and manufacturing milestones that come from talented engineers and semiconductor experts working in an open, collaborative environment with access to world class R&D facilities such as UAlbany NanoCollege's Albany NanoTech complex."

"This is a promising collaboration," said Mr. Shozo Saito, Corporate Senior Vice President of Toshiba Corporation and President & CEO of Toshiba's Semiconductor Company. "In addition to continuing the successful collaboration on fundamental advanced research, Toshiba will jointly develop the state-of-the-art 32nm bulk CMOS process integration technology, as a member of the world-class seven-company IBM Alliance. Concurrently we will also accelerate our own development of integration technology for the 32nm process at Toshiba's Advanced Microelectronics Center in Yokohama, toward achieving early production of leading-edge devices."

TOKYO--Toshiba Corporation today announced its entry into the emerging market for NAND-flash-based solid state drive (SSD) with a series of products featuring multilevel-cell NAND flash memories. Offered in a range of form factors and densities, Toshiba's solid state drives are designed primarily for notebook PCs. They will be showcased at the Consumer Electronics Show in Las Vegas, from January 7^th to 10^th. Samples and mass production will follow from the first quarter (January to March) of next year.

Moving NAND-based storage architecture forward, Toshiba's first solid state drives offer three densities: 32 gigabytes (GB), 64GB and 128GB. SSD realize low power consumption, a fast boot time, and lightweight, but market penetration has been held back by low densities and high prices. Toshiba's new SSD integrate an original MLC controller supporting fast read-write speeds, parallel data transfers and wear leveling, and achieve performance levels comparable to those of single-level NAND flash SSD. By applying MLC technology, Toshiba has realized a 128GB density in a 1.8 inch form factor. Toshiba expects the launch of its SSD line-up to speed up acceptance of solid state memory in laptops and digital consumer products, and to widen the horizons of the NAND flash market.

The new products utilize NAND flash memory fabricated with 56nm process technology, along with controller chips and DRAM, on a 70.6mm (L) x 53.6mm (W) x 3.0mm (H) platform. The maximum read speed is 100MB a second, and the maximum write speed of 40MB a second with the SATA2 interface (transfer rate of 3Gbps), which is compliant with high speed serial interface. The operating life is 1,000,000 hours^*1.

Outline of the new products

Product specification