The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit phase accumulator. The more significant bits of this provide 16 bits of phase accuracy for the sine and cosine look up tables.
With a 20 MHz system clock, waveforms up to 10 MHz can be produced, with 0.001 Hz resolution. If frequency modulation is required with no discontinuities, the phase increment value can be changed linearly on every clock cycle. Alternatively absolute phase jumps can be made to any phase value.
The provision of two output multipliers allows the sine and cosine waveforms to be amplitude modulated with a 16 bit value present on the input port. This option can also be used to generate the in-phase and quadrature components from an incoming signal. This I/Q split function is required by systems which employ complex signal processing.

*Direct Digital Synthesiser producing simultaneous sine and cosine values
*16 bit phase and amplitude accuracy, giving spur levels down to - 90 dB
*Synthesised outputs from DC to 10 MHz with accuracies better than 0.001 Hz
*Amplitude and Phase modulation modes
*84 pin PGA or 132 pin QFP

*Numerically controlled oscillator (NCO)
*Quadrature signal generator
*FM, PM, or AM signal modulator
*Sweep Oscillator
*High density signal constellation applications with simultaneous amplitude and phase modulation
*VHF reference for UHF generators
*Signal demodulator

PDSP16350/B0/AC, PDSP16350/B0/GC, PDSP16350/A0/AC, PDSP16350/A0/GC

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The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners.
Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable.
Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency.

*Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application
*2.2GHz up-synthesiser optimised for low phase noise up to comparison frequencies of 4MHz
*1.3GHz down-synthesiser optimised for low phase noise AND small step size
*Common reference oscillator and divider with independently selectable ratios for each synthesiser
*10:1 programmable charge pump current ratio in up synthesiser
*3-Wire bus programmable, each synthesiser indepently addressable
*Low power consumption, typ 100mW at 5V
*ESD protection, (Normal ESD handling procedures should be observed)

*TV, VCR, and cable tuning systems

SP5848/KG/QP1S, SP5848/KG/QP1T
TAG dual, PLL

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The ZL30402 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST-BUS and GCI backplanes.
The ZL30402 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30402 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.
The ZL30402 operates from a single 3.3 V power supply and offers a 5 V tolerant microprocessor interface.

*Meets requirements of GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC)
*Meets requirements of GR-1244 for stratum 3
*Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC)
*Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E2, E3, STM-1 and 19.44 MHz
*Holdover accuracy to 1x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements
*Continuously monitors Primary and Secondary reference clocks
*Provides “hit-less” reference switching
*Compensates for Master Clock Oscillator accuracy
*Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz,
1.544 MHz, 2.048 MHz and 19.44 MHz reference frequencies.
*Allows Hardware or Microprocessor control
*Pin compatible with MT90401 device.

*Synchronization for SDH and SONET Network Elements
*Clock generation for ST-BUS and GCI backplanes

ZL30402/QCC, ZL30402QCC1

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The ZL60214 video IP surveillance camera cable extender module is a fully integrated device designed for direct connection between two types of media, 10/100Base-TX (Fast Ethernet on shielded/unshielded twisted pair copper cables (STP/UTP) and 100Base-FX (Fast Ethernet on multi-mode fiber) with single fiber, to extend the network reach up to 2 km.
The Link is based on Zarlink’s world class family of high-performance LEDs, VCSELs and PINs and have been optimized to offer excellent optical coupling efficiency in combination with high bandwidth operation and extremely good reliability.
The optical part of the modules uses dichronic beamsplitters for maximum optical power budget and minimum crosstalk. Minimum internal crosstalk is achieved by the use of wavelength-selective detectors.
The Modules is designed for multi-mode fiber and optimized for 62.5/125 μm fiber.
The link offers attractive advantages in terms of weight and flexibility that allows the device to be attached directly to the copper cable and fit inside the outdoor protective housing for the IP camera.
Power supply of 100 to 230 V AC.
The part is compliant to the EU directive 2002/95/EC issued 27 January 2003 [RoHS] with exception number 6.

*Full duplex communication over single stranded multi-mode fiber
*Transmission distance: Ethernet up to 100 m, multi-mode fiber up to 2 km
*Compact size: 14-ports in 19" 1u rack
*Power 100-230V AC
*One single ST Fiber connector per 100Base-FX fiber cable
*TX: 850 nm, RX: 1300 nm

*10/100 Mbps extended LAN distances between:
-LAN and local IP surveillance cameras
-LAN and local access points for wireless IP cameras
-Remote switches and IP cameras
-Remote switches and access points for IP cameras


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The ZL70101 is a high performance half duplex RF communications link for medical implantable
The system is very flexible and supports several low power wakeup options. Extremely low power is achievable using the 2.45 GHz ISM Band Wakeupreceiver option. The high level of integration includes a Media Access Controller, providing complete control of the device along with coding and decoding of RF messages. A standard SPI interface provides for easy access by the application.

*402-405 MHz (10 MICS channels) and 433-434 MHz (2 ISM channels)
*High data rate (800/400/200 kbps raw data rate)
*High performance MAC with automatic error handling and flow control, typ < 1.5x10-10 BER.
*Very few external components (3 pcs + antenna matching)
*Extremely low power consumption (5 mA, continuous TX / RX, 1 mA low power mode)
*Ultra low power wakeup circuit (250 nA)
*Standards compatible (MICS, FCC, IEC)

*Implantable Devices e.g., Pacemakers, ICD’s, Neurostimulators, Implantable Insulin Pumps,
Bladder Control Devices, implantable physiological monitors
*Body area network, short range device applications using the 433 MHz ISM band.

ZL70101LDG1, ZL70101UBJ

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The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.

*Full duplex transmission over a single twisted pair
*Selectable 80 or 160 kbit/s line rate
*Adaptive echo cancellation
*Up to 3 km (9171) and 4 km (9172)
*ISDN compatible (2B+D) data format
*Transparent modem capability
*Frame synchronization and clock extraction
*Zarlink ST-BUS compatible
*Low power (typically 50 mW), single 5 V supply

*Digital subscriber lines
*High speed data transmission over twisted wires
*Digital PABX line cards and telephone sets
*80 or 160 kbit/s single chip modem

MT9171/72AE, MT9171/72AN, MT9171/72AP, MT9171/72APR, MT9171/72ANR
MT9171/72AE1, MT9171/72AP1, MT9171/72AN1, MT9171/72APR1, MT9171/72ANR1

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The ZL38015 is a four channel Voice-Processor hardware platform designed to support advanced voice and digital signal processing applications available from Zarlink Semiconductor. The ZL38015 platform integrates Zarlink’s Voice Processor (ZVP) DSP Core with a number of internal peripherals including: 2 PCM ports, a 2048 tap Filter Co-processor, 2 Auxiliary Timers and a Watchdog Timer, 9 GPIO pins, UART, Slave SPI and Master SPI ports and a master/slave timing block.
The firmware products and manuals available at the release of this data sheet is the ZLS38233: 4 Channel Voice Echo Cancellor (VEC) with integrated DTMF Transceiver (Tx/Rx). If these applications do not meet your requirements, please contact your local Zarlink Sales Office for the latest firmware releases.

*100 MHz (200 MIPs) Zarlink voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller
*On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM
*2048 tap Filter co-processor shared across up to 16 separate functions in 128 tap increments
*Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
*Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25 MHz
*Watchdog and 2 auxiliary timers
*11 General Purpose Input/Output (GPIO) pins
*General purpose UART port
*Bootloadable for future Zarlink software upgrades
*External oscillator or crystal/ceramic resonator
*1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
*IEEE-1149.1 compatible JTAG port

*Wireless Local Loop base stations and controllers
*Voice telephony gateways
*Digital, VoIP based and wireless PBX systems
*Echo Canceller pools
*Customer Premise equipment
*Integrated access devices
*SOHO gateways


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The low thermal droop of this device allows baseband video transmission with minimum distortion.
The double-lens optical system provides for optimum coupling of power into the fiber.
It matches with the MF446 PIN Photodiode.

* 780nm Surface-Emitting LED
* 55MHz Bandwidth
* Designed for 62.5/125μm fiber
* Low thermal droop

* Baseband Video
* Sensors
* General Purpose

MF359 ST

TAG led

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This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office.
It provides simultaneous connections for up to 256 64 kbit/s channels.
Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream.
In addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels.

* 3.3 volt supply
* 5 V tolerant inputs and TTL compatible outputs.
* 256 x 256 channel non-blocking switch
* Accepts serial streams at 2.048 Mb/s
* Per-channel three-state control
* Patented per channel message mode
* Non-multiplexed microprocessor interface
* Zarlink ST-BUS compatible
* Low power consumption: typical 15 mW
* Pin compatible with the MT8980DP

* Key telephone systems
* PBX systems
* Small and medium voice switching systems

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 The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus.
The device provides the CPS (Common Part Sublayer) and SAR (Segmentation and Reassembly) engines.
The MT90502 has the capability of simultaneously processing 1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits).
The device can be connected directly to an H.110 compatible bus.
The TDM bus consists of 32 bi-directional serial data streams operating at 2.048, 4.096, or 8.192 Mbits/s.
The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential Pulse Code Modulation) traffic for packetisation.
For these two data formats, the device also implements silence suppression and comfort noise generation.
To support other voice compression algorithms, the MT90502 connects directly to commercially available DSPs through synchronous serial data streams.
The Variable Bit Rate (VBR) traffic is HDLC encapsulated and carried over the serial data streams.
The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a compliant UTOPIA Level 2 Multi-PHY port.
The MT90502 provides the capability of routing ATM cells to different UTOPIA interfaces, SAR engine or CPU.
This feature can be used to connect another MT90502 (to support up to 2046 CID channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR.

* AAL2 Segmentation Reassembly device capable of simultaneously processing up to 1023 active CIDs (AAL2 Channel Identifier) and 1023 active VCs (Virtual Circuits).
* Support for up to 255 CIDs per VC. Maximum of 1023 CIDs.
* Implements AAL2 Common Part Sub-layer (CPS) functions specified in ITU I.363.2.
* Implements AAL2 Service Specific Convergence Sub-layer (SSCS) functions for G.711 PCM and G.726 ADPCM voice.
* Supports 44-byte PCM or ADPCM packet profiles specified in AF-VMOA-0145.00.
* CPS packet payload can support up to 64-bytes.
* Supports over-subscription of 10:1.
* H.100/H.110 compatible TDM bus for PCM or ADPCM data. Supports both master and slave TDM bus clock operation.
* TDM bus also supports compressed voice such as ITU G.723, G.728 and G.729 through HDLC encapsulation.
* Three UTOPIA Level 1 ports configurable as PHY or ATM allowing for connection to an external AAL5 SAR processor, or for chaining multiple MT90502 devices. Ports A & B are configurable as a single 8-bit UTOPIA Level 2 PHY port with 5 ADDR lines.
* UTOPIA module provides a cell switching function with a header translation.
* Performs silence suppression for PCM and ADPCM.
* Comfort noise generation.
* Capability to inject and recover CPS packets through the CPU host processor bus.
* 8-bit or 16-bit microprocessor port, configurable to Motorola or Intel timing.
* Single rail 3.3 V, 456 PBGA.
* IEEE 1149 (JTAG) interface.

* Gateway
* ATM Edge Switch
* Next Generation Digital Loop Carrier
* Multiservice Switching Platform
* 3rd Generation Mobile System Equipment


TAG channel, Multi

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