Description
The Xc4010D and XC4013D are RAM-less, lower-cost versions of the XC4010 and XC4013. They are identical to the XC4010 and XC4013 in all respects, except for the missing on-chip RAM.
The XC4010D and XC4013D are available in most of the same PLCC, PQFP, and PGA packages as their corresponding XC4000 non-D equivalents. See page 2-70 for details.
The XC4010D and XC4013D are also pin-compatible with the XC5210 (see XC5200 Data Sheet for additional information). The XC5210 provides another possible cost-reduction path for lower-performance applications that do not use the XC4000D features like wide-decoders and carry logic.
For complete electrical specifications, see pages 2-47 through 2-55.
For a detailed description of the device features, architecture and configuration methods, see pages 2-9 through 2-45.
For a detailed list of package printouts, please use the cross-referance on page 2-70.
For package physical dimensions and thermal data, see Section 4.

Features
*Third Generation Field-Programmable Gate Array
–Abundant flip-flops
–Flexible function generators
–No on-chip RAM
–Dedicated high-speed carry-propagation circuit
–Wide edge decoders (four per edge)
–Hierarchy of interconnect lines
–Internal 3-state bus capability
–Eight global low-skew clock or signal distribution network
*Flexible Array Architecture
–Programmable logic blocks and I/O blocks
–Programmable interconnects and wide decoders
*Sub-micron CMOS Process
–High-speed logic and Interconnect
–Low power consumption
*Systems-Oriented Features
–IEEE 1149.1-compatible boundary-scan logic support
–Programmable output slew rate (2 modes)
–Programmable input pull-up or pull-down resistors
–12-mA sink current per output
–24-mA sink current per output pair
*Configured by Loading Binary File
–Unlimited reprogrammability
–Six programming modes
*XACT Development System runs on ’386/’486-type PC, Apollo, Sun-4, and Hewlett-Packard 700 series
–Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
–Fully automatic partitioning, placement and routing
–Interactive design editor for design optimization
–288 macros, 34 hard macros, RAM/ROM compiler

XC4010D, XC4013D
TAG Array, cell, Logic

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Description
The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation.
The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

Features
*Industry's first TotalCMOS™ SPLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and high speed
-Static current of less than 75 μA
-Dynamic current substantially below that of competing devices
-Pin-to-pin delay of only 7.5 ns
*True Zero Power device with no turbo bits or power down schemes
*Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s
*Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP)
-24-pin TSOIC–uses 93% less in-system space than a 28-pin PLCC
-24-pin SOIC
-28-pin PLCC with standard JEDEC pinout
*Available in commercial and industrial operating ranges
*Advanced 0.5μ E2CMOS process
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Varied product term distribution with up to 16 product terms per output for complex functions
*Programmable output polarity
*Synchronous preset/asynchronous reset capability
*Security bit prevents unauthorized access
*Electronic signature for identification
*Design entry and verification using industry standard CAE tools
*Reprogrammable using industry standard device programmers

XCR22V10-10SO24, XCR22V10-7SO24, XCR22V10-10VO24C, XCR22V10-7VO24C

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Description
The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 μA at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 1.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.0 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The XCR3064A CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).
The XCR3064A CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BPMicrosystems, SMS, and others. The XCR3064A also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.

Features
*Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
*3V, In-System Programmable (ISP) using a JTAG interface
-On-chip superVoltage generation
-ISP commands include: Enable, Erase, Program, Verify
-Supported by multiple ISP programming platforms
-Four pin JTAG interface (TCK, TMS, TDI, TDO)
-JTAG commands include: Bypass, Idcode
*High speed pin-to-pin delays of 7.5 ns
*Ultra-low static power of less than 100 μA
*5V tolerant I/Os to support mixed Voltage systems
*100% routable with 100% utilization while all pins and all macrocells are fixed
*Deterministic timing model that is extremely simple to use
*Up to 12 clocks with programmable polarity at every macrocell
*Support for complex asynchronous clocking
*Innovative XPLA™ architecture combines high speed with extreme flexibility
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Logic expandable to 37 product terms
*Advanced 0.35μ E2CMOS process
*Security bit prevents unauthorized access
*Design entry and verification using industry standard and Xilinx CAE tools
*Reprogrammable using industry standard device programmers
*Innovative Control Term structure provides either sum terms or product terms in each logic block for:
-Programmable 3-state buffer
-Asynchronous macrocell register preset/reset
-Up to two asynchronous clocks
*Programmable global 3-state pin facilitates `bed of nails' testing without using logic resources
*Available in PLCC, VQFP, and Chip Scale BGA packages
*Industrial grade operates from 2.7V to 3.6V

XCR3064A-7VQ44C, XCR3064A-10VQ44C, XCR3064A-12VQ44C, XCR3064A-7PC44C

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Description
Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-touse, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. A summary of the Platform Flash PROM family members and supported features is shown in Table 1.

Features
*In-System Programmable PROMs for Configuration of Xilinx® FPGAs
*Low-Power Advanced CMOS NOR Flash Process
*Endurance of 20,000 Program/Erase Cycles
*Operation over Full Industrial Temperature Range (–40°C to +85°C)
*IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
*JTAG Command Initiation of Standard FPGA Configuration
*Cascadable for Storing Longer or Multiple Bitstreams
*Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
*I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
*Design Support Using the Xilinx Alliance ISE® and Foundation™ ISE Series Software Packages
*XCF01S/XCF02S/XCF04S
-3.3V Supply Voltage
-Serial FPGA Configuration Interface (up to 33 MHz)
-Available in Small-Footprint VO20 and VOG20 Packages
*XCF08P/XCF16P/XCF32P
-1.8V Supply Voltage
-Serial or Parallel FPGA Configuration Interface(up to 33 MHz)
-Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages
-Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for
Configuration
-Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

XCF02S, XCF04S, XCF08P, XCF16P, XCF32P

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Description
Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM. The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that
require operation over the full military temperature range.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data
is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are
interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration
PROMs.

Features
*Operating Temperature Range: –55° C to +125°C
*Low-power advanced CMOS FLASH process memory cells immune to static single event upset
*In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
*IEEE Std 1149.1 boundary-scan (JTAG) support
*Cascadable for storing longer or multiple bitstreams
*Dual configuration modes
- Serial Slow/Fast configuration (up to 20 MHz)
- Parallel (up to 160 Mbps at 20 MHz)
*5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
*3.3V or 2.5V output capability
*Available in plastic VQ44 packaging only
*Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages
*JTAG command initiation of standard FPGA configuration

XQV300, XQV600, XQV1000

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Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.
A total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.

Features
*Lowest power 32 macrocell CPLD
*5.0 ns pin-to-pin logic delays
*System frequencies up to 200 MHz
*32 macrocells with 750 usable gates
*Available in small footprint packages
-48-ball CS BGA (36 user I/O pins)
-44-pin VQFP (36 user I/O)
-44-pin PLCC (36 user I/O)
*Optimized for 3.3V systems
-Ultra-low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35 micron five layer metal EEPROM process
-Fast Zero Power™ (FZP) CMOS design technology
*Advanced system features
-In-system programming
-Input registers
-Predictable timing model
-Up to 23 available clocks per function block
-Excellent pin retention during design changes
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
-Four global clocks
-Eight product term control terms per function block
*Fast ISP programming times
*Port Enable pin for dual function of JTAG ISP pins
*2.7V to 3.6V supply voltage at industrial temperature range
*Programmable slew rate control per macrocell
*Security bit prevents unauthorized access
*Refer to XPLA3 family data sheet (DS012) for architecture description

XCR3032XL-5VQ44C
XCR3032XL-10VQ44C

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Description
The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved
This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt-trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis.
This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.
Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.

Features
* AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
* Guaranteed to meet full electrical specifications over TA = -40°C to +105°C with TJ Maximum = +125°C (Q-grade)
* Optimized for 1.8V systems
* Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
* Available in the following package options
- 100-pin VQFP with 80 user I/O
- 132-ball CP (0.5mm) BGA with 100 user I/O
- Pb-free only for all packages

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Description
 Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs.
Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.
New data is available a short access time after each rising clock edge.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM.
When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins.
New data is available a short access time after each rising clock edge.
The data is clocked into the FPGA on the following rising edge of the CCLK.
A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
- Endurance of 20,000 Program/Erase Cycles
- Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
* IEEE Std 1149.1 Boundary-Scan (JTAG) Support
* JTAG Command Initiation of Standard FPGA Configuration
* Simple Interface to the FPGA
* Cascadable for Storing Longer or Multiple Bitstreams
* Low-Power Advanced CMOS FLASH Process
* Dual Configuration Modes
- Serial Slow/Fast Configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
* 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
* 3.3V or 2.5V Output Capability
* Design Support Using the Xilinx ISE™ Foundation™ Software Packages
* Available in PC20, SO20, PC44, and VQ44 Packages
* Lead-Free (Pb-Free) Packaging

XC18V04
XC18V02
XC18V01
XC18V512

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Description
 The CoolRunner™-II Automotive 32-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved.
This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
The CoolRunner-II Automotive 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33.
This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O banking.
Two I/O banks are available on the CoolRunner-II Automotive 32-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Features
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over TA = -40° C to +105° C with TJ Maximum = +125° C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
• Available in Pb-free 44-pin VQFP with 33 user I/O
• Advanced system features
- Fastest in system programming
 · 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
 · Optional DualEDGE triggered registers
- Global signal options with macrocell control
 · Multiple global clocks with phase selection per macrocell
 · Multiple global output enables
 · Global set/reset
- Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- PLA architecture
 · Superior pinout retention
 · 100% product term routability across function block
- Hot pluggable
Refer to the CoolRunner™-II Automotive CPLD family data sheet for architecture description.

XA2C32A-6VQG44I
XA2C32A-7VQG44Q

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