DESCRIPTION
The TPS65573 offers a complete solution for a charging photo flash capacitor and flashing xenon tube with insulated gate bipolar transfer (IGBT) driver. This device has an integrated voltage reference, power (SW), comparators for peak current detection/power SW turnon detection/charge complete detection, IGBT driver and control logics for charging applications/driving IGBT applications.
Compared with discrete solutions, this device reduces the component count, shrinks the total solution size, and erases the difficulty of design for xenon tube application.
Additional advantages are a fast charging time and high efficiency since this device has an optimized pulse width modulation (PWM) control algorithm for photo flash charging. Also this device has high accuracy for peak current detection and for charge completion detection. The distribution of charging time is smaller.
Other provisions of the device include sensing the output voltage at the primary side, programmable peak current at the primary side, protection features (thermal shutdown and overcurrent), an output pin for charge completion detection, input pins for charge enable, flash acceptable, and flash on.

FEATURES
*Wide Input Voltage
-VBAT = 1.4 V to 12 V
-VCC = 2.5 V to 5.5 V
*Integrated 50-V Power Switch With Lower R ON
*Programmable Peak Current at Primary Side From 0.5 A to 1.5 A
*Optimized Switch ON/OFF Control for Fast Charging
*Charge Complete Detection at Primary Side With High Accuracy
*Integrated IGBT Driver
*2-mm × 3-mm, 12-Pin WSON Package
*Protection
-Overcurrent Protection (OCP)
-Thermal Shutdown (TSD)

APPLICATIONS
*Digital Still Cameras
*Optical Film Cameras
*Digital Video Camcorders
*Cell Phones

TPS65573DSST, TPS65573DSSR

DESCRIPTION
The UCD9220 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop
management with flash memory and a serial interface to support configuration, monitoring and management.
The UCD9220 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

FEATURES
*Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM Controller
*Controls Up To Two Voltage Rails and Up To Four Phases
*Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
*Up To 1mV Closed Loop Resolution
*Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain for Improved Transient Performance
*Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up
*Supports Voltage Tracking, Margining and Sequencing
*Supports Current and Temperature Balancing for Multi-Phase Power Stages
*Supports Phase Adding/Shedding for Multi-Phase Power Stages
*Sync In /Out Pins Align DPWM Clocks Between Multiple UCD9220 Devices
*12-Bit Digital Monitoring of Power Supply Parameters Including:
-Input Current and Voltage
-Output Current and Voltage
-Temperature at Each Power Stage
*Multiple Levels of Overcurrent Fault Protection:
-External Current Fault Inputs
-Analog Comparators Monitor Current Sense Voltage
-Current Digitally Monitored
*Over and Undervoltage Fault Protection
*Overtemperature Fault Protection
*Enhanced Nonvolatile Memory With Error Correction Code (ECC)
*Device Operates From a Single Supply With an Internal Regulator Controller That Allows Operation Over a Wide Supply Voltage Range
*Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS
*Industrial/ATE
*Networking Equipment
*Telecommunications Equipment
*Servers
*Storage Systems
*FPGA, DSP and Memory Power

UCD9220RGZR, UCD9220RGZT

DESCRIPTION
The ADS1675 is a high-speed, high-precision analog-to-digital converter (ADC). Using an advanced delta-sigma (ΔΣ) architecture, it operates at speeds up to 4MSPS with outstanding ac performance and dc accuracy.
The ADS1675 ADC is comprised of a low-drift modulator with out-of-range detection and a dual-path programmable digital filter. The dual filter path allows the user to select between two post-processing filters: Low-Latency or Wide-Bandwidth. The Low-Latency filter settles quickly (as fast as 2.65ms) for applications with large instantaneous changes, such as a multiplexer. The Wide-Bandwidth path provides an optimized frequency response for ac measurements with a passband ripple of less than 0.00002dB, stop band attenuation of 115dB, and a bandwidth of 1.7MHz.
The device offers two speed modes with distinct interface, resolution, and feature set. In the
high-speed mode the device can be set to operate at either 4MSPS or 2MSPS. In the low-speed mode, it can be set to operate at either 1MSPS, 500KSPS, 250KSPS or 125KSPS.
The ADS1675 is controlled through I/O pins—there are no registers to program. A dedicated START pin allows for direct control of conversions: toggle the START pin to begin a conversion, and then retrieve the output data. The flexible serial interface supports data readback with either standard CMOS and LVDS logic levels, allowing the ADS1675 to directly connect to a wide range of microcontrollers, digital signal processors (DSPs), or field-programmable grid arrays FPGAs).
The ADS1675 operates from an analog supply of 5V and digital supply of 3V, and dissipates 575mW of power. When not in use, the PDWN pin can be used to power down all device circuitry. The device is fully specified over the industrial temperature range and is offered in a TQFP-64 package.

FEATURES
*AC Performance: 103dB of Dynamic Range at 4MSPS, 111dB of Dynamic Range at 125kSPS
-107dB THD
*DC Accuracy: 3ppm INL, 4mV/°C Offset Drift, 4ppm/°C Gain Drift
*Programmable Digital Filter with User-Selectable Path:
–Low-Latency: Completely settles in 2.65ms
–Wide-Bandwidth: 1.7MHz BW with flat passband
*Flexible Read-Only Serial Interface:
–Standard CMOS
–Serialized LVDS
*Easy Conversion Control with START Pin
*Out-of-Range Detection
*Supply: Analog +5V, Digital +3V
*Power: 575mW

APPLICATIONS
*Automated Test Equipment
*Medical Imaging
*Scientific Instrumentation
*Test and Measurement

ADS1675IPAG, ADS1675IPAGR

DESCRIPTION
The TPA6141A2 (also known as TPA6141) is a Class-G DirectPath™ stereo headphone amplifier with selectable gain. Class-G technology maximizes battery life by adjusting the voltage supplies of the headphone amplifier based on the audio signal level. At low level audio signals, the internal supply voltage is reduced to minimize power dissipation. DirectPathTM technology eliminates external DC-blocking capacitors.
The device operates from a 2.5 V to 5.5 V supply voltage. Class-G operation keeps total supply current below 5.0 mA while delivering 500 mW per channel into 32 Ω. Shutdown mode reduces the supply current to less than 3 mA and is activated through the EN pin.
The device has built-in pop suppression circuitry to completely eliminate disturbing pop noise during turn-on and turn-off. The amplifier outputs have short-circuit and thermal-overload protection along with ±8 kV HBM ESD protection, simplifying end equipment compliance to the IEC 61000-4-2 ESD standard.
The TPA6141A2 (TPA6141) is available in a 0,4 mm pitch, 16-bump 1,6 mm × 1,6 mm WCSP (YFF) package.

FEATURES
*TI Class-G Technology Significantly Prolongs Battery Life and Music Playback Time
–0.6 mA / Ch Quiescent Current
–50% to 80% Lower Quiescent Current Than Ground-Referenced Class-AB Headphone Amplifiers
*DirectPathTM Technology Eliminates Large Output DC-Blocking Capacitors
–Outputs Biased at 0 V
–Improves Low Frequency Audio Fidelity
*Active Click and Pop Suppression
*Fully Differential Inputs Reduce System Noise
–Also Configurable as Single-Ended Inputs
*SGND Pin Eliminates Ground Loop Noise
*Wide Power Supply Range: 2.5 V to 5.5 V
*100 dB Power Supply Noise Rejection
*Gain Settings: 0 dB and 6dB
*Short-Circuit Current Limiter
*Thermal-Overload Protection
*±8 kV HBM ESD Protected Outputs
*0,4 mm Pitch, 1,6 mm × 1,6 mm WCSP Package

APPLICATIONS
*Cellular Phones / Music Phones
*Portable Media / MP3 Players
*Portable CD / DVD Players

TPA6141A2YFFR, TPA6141A2YFFT

DESCRIPTION
The TAS5352A is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4-Ω bridge-tied load (BTL) at up to 125 W per channel with low harmonic distortion, low integrated noise, and low idle current.
The TAS5352A has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of PWM signal (PWM activity detector).
A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs.

FEATURES
*Total Power Output (Bridge Tied Load)
-2 × 125 W at 10% THD+N Into 4 Ω
-2 × 100 W at 10% THD+N Into 6 Ω
*Total Power Output (Single Ended)
-4 × 45 W at 10% THD+N Into 3 Ω
-4 × 35 W at 10% THD+N Into 4 Ω
*Total Power Output (Parallel Mode)
-1 × 250 W at 10% THD+N Into 2 Ω
-1 × 195 W at 10% THD+N Into 3 Ω
*>110 dB SNR (A-Weighted With TAS5518 Modulator)
*<0.1% THD+N (1 W, 1 kHz)
*Supports PWM Frame Rates of 192 kHz to 432 kHz
*Resistor-Programmable Current Limit
*Integrated Self-Protection Circuitry, Including:
-Under Voltage Protection
-Overtemperature Warning and Error
-Overload Protection
-Short-Circuit Protection
-PWM Activity Detector
*Standalone Protection Recovery
*Power-On Reset (POR) to Eliminate System Power-Supply Sequencing
*High-Efficiency Power Stage (>90%) With 80-mΩ Output MOSFETs
*Thermally Enhanced 44-Pin HTSSOP Package (DDV)
*Error Reporting, 3.3-V and 5.0-V Compliant
*EMI Compliant When Used With Recommended System Design

APPLICATIONS
*Mini/Micro Audio System
*DVD Receiver
*Home Theater

TAS5352ADDV

DESCRIPTION
The SN75LVCP412 is a dual channel, single lane SATA redriver and signal conditioner supporting data rates up to 3.0 Gbps. The device complies with SATA specification revision 2.6 and eSATA requirements.
The SN75LVCP412 operates from a single 3.3-V supply and has 100-Ω line termination with self-biasing feature making the device suitable for AC coupling. The inputs incorporate an OOB detector, which automatically squelches the output while maintaining a stable output common-mode voltage compliant to SATA link. The device is also designed to handle SSC transmission per the SATA specification.
The SN75LVCP412 handles interconnect losses at both its input and output. The built-in transmitter pre-emphasis feature is capable of applying 0 dB or 2.5 dB of relative amplification at higher frequencies to counter the expected interconnect loss. On the receive side the device applies a fixed equalization of 7 dB to boost input frequencies near 1.5 GHz. Collectively, the input equalization and output pre-emphasis features of the device work to fully restore SATA signal integrity over extended cable and backplane pathways.
The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal.

FEATURES
*Data Rates up to 3.0 Gbps
*SATA Gen 2.6, eSATA Compliant
*SATA Hot-Plug Capable
*Supports Common-Mode Biasing for OOB Signaling with Fast Turn-On
*Channel Selectable Pre-Emphasis
*Fixed Receiver Equalization
*Integrated Termination
*Low Power
– <200 mW Typ
– <5 mW (in sleep mode)
*Excellent Jitter and Loss Compensation Capability to Over 20 Inch FR4 Trace
*20-Pin 4 × 4 QFN Package

APPLICATIONS
*Notebooks, Desktops, Docking Stations, Servers, Workstations

SN75LVCP412RTJR

DESCRIPTION
The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.
The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is
provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

FEATURES
*Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM
Controller
*Controls Up To Four Voltage Rails and Up To Eight Phases
*Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
*Up To 1mV Closed Loop Resolution
*Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain for
Improved Transient Performance
*Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up
*Supports Voltage Tracking, Margining and Sequencing
*Supports Current and Temperature Balancing for Multi-Phase Power Stages
*Supports Phase Adding/Shedding for Multi-Phase Power Stages
*Sync In /Out Pins Align DPWM Clocks Between Multiple UCD9240 Devices
*Fan Monitoring and Control
*12-Bit Digital Monitoring of Power Supply Parameters Including:
– Input Current and Voltage
– Output Current and Voltage
– Temperature at Each Power Stage
*Multiple Levels of Overcurrent Fault Protection:
– External Current Fault Inputs
– Analog Comparators Monitor Current Sense Voltage
– Current Continually Digitally Monitored
*Over and Undervoltage Fault Protection
*Overtemperature Fault Protection
*Enhanced Nonvolatile Memory With Error Correction Code (ECC)
*Device Operates From a Single Supply With an Internal Regulator Controller That Allows
Operation Over a Wide Supply Voltage Range
*Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design
Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS
*Industrial/ATE
*Networking Equipment
*Telecommunications Equipment
*Servers
*Storage Systems
*FPGA, DSP and Memory Power

UCD9240PFCR, UCD9240PFC

Description
The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x™ DSP core. It provides significantly lower power than other members of the  MS320C6000™ platform of DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an synchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Features
*Applications
- Industrial Control
- USB, Networking
- High-Speed Encoding
- Professional Audio
*Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
*Dual Core SoC
– 300-MHz ARM926EJ-S™ RISC MPU
– 300-MHz C674x™ VLIW DSP
*ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
*ARM9 Memory Architecture
*C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
*C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
*Enhanced Direct-Memory-Access Controller 3 (EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
*TMS320C674x™ Floating Point VLIW DSP Core
– LSouapdp-oSrttore Architecture With Non-Aligned
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
– Two Multiply Functional Units
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and Program Redirecrion
*128K-Byte RAM Shared Memory
*Two External Memory Interfaces:
– EMIFA
– EMIFB
*Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
*LCD Controller
*Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
*Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
*Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
*USB 1.1 OHCI (Host) With Integrated PHY (USB1)
*USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
*Three Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capavle (McASP2)
- FIFO buffers for Transmit and Receive
*10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
*One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
*Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
*One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
*One 64-Bit General-Purpose Timer (Watch Dog)
*Three Enhanced Pulse Width Modulators (eHRPWM):
– Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
*Three 32-Bit Enhanced Capture Modules (eCAP):
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator(APWM)outputs
- Single Shot Capture of up to Four Event Time-Stamps
*Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
*256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
*Commercial or Extended Temperature

OMAPL137ZKB3, XOMAPL137ZKB3

DESCRIPTION
The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference.
Different modes of operation enable or bypass various signal processing blocks.
The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.
The DAC5688 dual CMOS data bus provides 250MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing.
Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.
The DAC5688 allows both complex or real output.
An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair.
A digital Inverse SINC filter compensates for natural DAC Sin(X)/X frequency roll-off.
The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.
The DAC5688 is characterized for operation over the industrial temperature range of -40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

FEATURES
* Dual, 16-Bit, 800 MSPS DACs
* Dual, 16-Bit, 250 MSPS CMOS Input Data
- 16 Sample Input FIFO
- Flexible input data bus options
* High Performance
- 81 dBc ACLR WCDMA TM1 at 70 MHz
* 2x-32x Clock Multiplying PLL/VCO
* Selectable 2x–8x Interpolation Filters
- Stop-band Attenuation > 80 dB
* Complex Mixer with 32-Bit NCO
* Digital Quadrature Modulator Correction
- Gain, Phase and Offset Correction
* Digital Inverse SINC Filter
* 3- or 4-Wire Serial Control Interface
* On Chip 1.2-V Reference
* Differential Scalable Output: 2 to 20 mA
* Package: 64-pin 9´9mm QFN

APPLICATIONS
* Cellular Base Stations
* Broadband Wireless Access (BWA)
* WiMAX 802.16
* Fixed Wireless Backhaul
* Cable Modem Termination System (CMTS)

DESCRIPTION
 The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an MSOP-10 package.
The PGA116 and PGA117 (binary/scope fains) offer 10 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software shutdown in a TSSOP-20 package.
All versions provide internal calibration channels for system-level calibration.
The channels are tied to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively.
VCAL, an external voltage connected to Channel 0, is used as the system calibration reference.
Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5,10, 20, 50, 100, and 200.

FEATURES
* Rail-to-Rail Input/Output
* Offset: 25mV (typ), 100mV (max)
* Zerø Drift: 0.35mV/°C (typ), 1.2mV/°C (max)
* Low Noise: 12nV/√Hz
* Input Offset Current: ±5nA max (+25°C)
* Gain Error: 0.1% max (G ≤ 32), 0.3% max (G > 32)
* Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
* Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
* Gain Switching Time: 200ns
* Two Channel MUX: PGA112, PGA113
  10 Channel MUX: PGA116, PGA117
* Four Internal Calibration Channels
* Amplifier Optimized for Driving CDAC ADCs
* Output Swing: 50mV to Supply Rails
* AVDD and DVDD for Mixed Voltage Systems
* IQ = 1.1mA (typ)
* Software/Hardware Shutdown: IQ ≤ 4mA (typ)
* Temperature Range: –40°C to +125°C
* SPI™ Interface (10MHz) with Daisy-Chain Capability

APPLICATIONS
* Remote e-Meter Reading
* Automatic Gain Control
* Portable Data Acquisition
* PC-Based Signal Acquisition Systems
* Test and Measurement
* Programmable Logic Controllers
* Battery-Powered Instruments
* Handheld Test Equipment

PGA113
PGA116
PGA117