Description
The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL® technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter, low-power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C).

Features
Complete CDR solution includes the following:
*Supports OC-12/3, STM-4/1
*Low power, 293 mW (TYP OC-12)
*Small footprint: 4x4 mm
*DSPLL™ eliminates external loop filter components
*3.3 V tolerant control inputs
*Exceeds All SONET/SDH jitter specifications
*Jitter generation 1.6 mUIrms (typ)
*Device powerdown
*Loss-of-lock indicator
*Single 2.5 V supply

Applications
*SONET/SDH/ATM routers
*Add/drop multiplexers
*Digital cross connects
*Board level serial links
*SONET/SDH test equipment
*Optical transceiver modules
*SONET/SDH regenerators

Si5010-BM, Si5010-GM

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Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Features
*Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
*Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs w/manual or automatically controlled hitless switching
*Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
*Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
*LOL, LOS, FOS alarm outputs
*Digitally-controlled output phase adjust
*I2C or SPI programmable
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size: 6 x 6 mm 36-lead QFN
*Pb-free, ROHS compliant

Applications
*SONET/SDH OC-48/OC-192 line cards
*GbE/10GbE, 1/2/4/8/10GFC line cards
*ITU G.709 and custom FEC line cards
*Optical modules
*Wireless basestations
*Data converter clocking
*xDSL
*SONET/SDH + PDH clock synthesis
*Test and measurement

Si5326A-B-GM, Si5326B-B-GM, Si5326C-B-GM

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Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si533 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si533 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si533 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators.

Features
*Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz
*2 selectable output frequencies
*3rd generation DSPLL® with superior jitter performance
*3x better frequency stability than SAW-based oscillators
*Pin 1 output enable (OE)
*Internal fixed crystal frequency ensures high reliability and low aging
*Available CMOS, LVPECL, LVDS, and CML outputs
*3.3, 2.5, and 1.8 V supply options
*Industry-standard 5 x 7 mm package and pinout
*Pb-free/RoHS-compliant

Applications
*SONET/SDH
*Networking
*SD/HD video
*Clock and data recovery
*FPGA/ASIC clock generation

SI533AA00100DGR, SI533BA00100DGR, SI533CA00100DGR, SI533DA00100DGR

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Description
The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/port cards. This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock). Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. The on-chip reference monitoring and clock switching functions support Stratum 3/3E and SMC compatible clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios. The Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation. It operates from a single 3.3 V supply.

Features
*Ultra-low jitter clock outputs with jitter generation as low as 0.3 psRMS
*No external components (other than a resistor and standard bypassing)
*Up to three clock inputs
*Four independent clock outputs at 19, 155, or 622 MHz
*Stratum 3, 3E, and SMC compatible
*Digital hold for loss-of-input clock
*Automatic or manually-controlled hitless switching between clock inputs
*Revertive/non-revertive switching
*Loss-of-signal and frequency offset alarms for each clock input
*Support for forward and reverse FEC clock scaling
*8 kHz frame sync output
*Low power
*Small size (11x11 mm)

Applications
*SONET/SDH line/port cards
*Terabit routers
*Core switches
*Digital cross connects

Si5364-F-BC

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Description
The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is ideal for providing jitter attenuation in high performance timing applications.

Features
*Fixed frequency jitter attenuator with selectable clock ranges at 19, 38, 77, 155, 311, and 622 MHz (710 MHz max)
*Support for SONET, 10GbE, 10GFC, and corresponding FEC rates
*Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (100 Hz to 7.9 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs with integrated clock select mux
*One clock input can be 1x, 4x, or 32x the frequency of the second clock input
*Single clock output with selectable signal format: LVPECL, LVDS, CML, CMOS
*LOL, LOS alarm outputs
*Pin programmable settings
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size (6 x 6 mm 36-lead QFN)
*Pb-free, RoHS compliant

Applications
*Optical modules
*SONET/SDH OC-48/OC-192 line cards
*10GbE, 10GFC line cards
*ITU G.709 line cards
*Wireless basestations
*Test and measurement

Si5316-B-GM

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Description
The Si4720/21 is the first single chip FM radio transceiver. The proven and patented digital architecture of the Si4720/21 combines the functionality of the Si470x FM radio receiver with the Si471x FM transmitter, offering full FM receive and transmit capabilities in a single, ultra-small 3x3x0.55 mm QFN package. The device leverages Silicon Lab's highly successful and proven FM technology, and offers unmatched integration and performance allowing FM receive and transmit to be added to any portable device by using a single chip. As with the Si470x and Si471x products, the Si4720/21 offers industry leading size, performance, low power consumption, and ease of use.
The Si4720/21's digital integration reduces the required external components of traditional offerings, resulting in a solution requiring only an external inductor and bypass capacitor, and a PCB space of approximately 15 mm2. The Si4720/21 is layout compatible with Silicon Laboratories' Si470x FM radio receivers, Si473x AM/FM radio receivers, and the Si471x FM radio transmitter solutions, allowing a single PCB layout to accommodate a variety of music features. High yield manufacturability, unmatched performance, easy design-in, and software programmability are key advantages of the Si4720/21.
The Si4721 is the industry's first single-chip integrated FM radio transceiver including both receive and transmit support for the European Radio Data System (RDS) and the U.S. Radio Broadcast Data System (RBDS). RDS allows digital information sent from the broadcaster to be displayed, such as station ID, song name and music category. In Europe, alternate frequency (AF) information is also provided to automatically change stations in areas where broadcasters use multiple frequencies. In transmit mode, digital information such as artist name, song title, music category, and branded messaging can be transmitted and displayed on any RDS/RBDS receiver.
Users are responsible to adjust their system's radiated power levels to comply with local regulations on RF transmission (FCC, ETSI, ARIB, etc.).

Features
*Integrated FM antenna support
*Excellent real-world performance
*Only two external components required
*Worldwide FM band support (76 to 108 MHz)
*RDS/RBDS processor (Si4721)
*Frequency synthesizer with integrated VCO
*Adjustable seek parameters
*Adjustable mono/stereo blend
*Adjustable soft mute
*Programmable transmit output voltage control
*Audio dynamic range control
*Advanced modulation control
*Analog/digital audio interface
*Programmable reference clock input
*Programmable pre/de-emphasis (50/75 μs)
*2-wire and 3-wire control interface
*Integrated LDO regulator
*2.7 to 5.5 V supply voltage
*3x3x0.55 mm 20-pin Pb-free QFN package

Applications
*Cellular handsets/hands free
*MP3 players
*Portable media players
*GPS/navigation devices
*Satellite digital audio radios
*Personal computers

SI4721

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Description
The Si2401 ISOmodem® is a complete, two-chip, 2400 bps modem integrating Silicon Laboratories’ fourth-generation direct access arrangement (DAA), which provides a globally-programmable telephone line interface with an unprecedented level of integration. Available in two small packages, this compact solution eliminates the need for a separate DSP data pump, modem controller, codec, isolation transformer, relay, opto-isolators, and 2–4 wire hybrid. The Si2401 provides conventional data formats at connect rates of up to 2400 bps with full-duplex operation over the Public Switched Telephone Network (PSTN). This device is ideal for embedded modem applications due to its small size, minimal external component count, and low power consumption.

Features
*Data modem formats
-2400 bps: V.22bis
-1200 bps: V.22, V.23, Bell 212A
-300 bps: V.21, Bell 103
-Fast connect and V.23 reversing
-SIA and other security protocols
*27 MHz CLKIN support
*Caller ID detection and decode
*UART with flow control
*Integrated DAA
-Over 6000 V capacitive isolation
-Parallel phone detection
-Compliant with FCC, China, JATE, and 31 other PTTs
-Line-in-use detection
*AT command set support
*Call progress support
*3.3 V Power
*Lead-free and RoHS-compliant packages

Applications
*Set-top boxes
*Point-of-sale
*ATM terminals
*Security systems
*Medical monitoring
*Power meters

Si3008, SI2401-FS, SI3008-B-FS

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Description
The Si2401 ISOmodem® is a complete, two-chip, 2400 bps modem integrating Silicon Laboratories’ fourth-generation direct access arrangement (DAA), which provides a globally-programmable telephone line interface with an unprecedented level of integration. Available in two small packages, this compact solution eliminates the need for a separate DSP data pump, modem controller, codec, isolation transformer, relay, opto-isolators, and 2–4 wire hybrid. The Si2401 provides conventional data formats at connect rates of up to 2400 bps with full-duplex operation over the Public Switched Telephone Network (PSTN). This device is ideal for embedded modem applications due to its small size, minimal external component count, and low power consumption.

Features
*Data modem formats
 2400 bps: V.22bis
 1200 bps: V.22, V.23, Bell 212A
 300 bps: V.21, Bell 103
 Fast connect and V.23 reversing
 SIA and other security protocols
*27 MHz CLKIN support
*Caller ID detection and decode
*UART with flow control
*Integrated DAA
 Over 6000 V capacitive isolation
 Parallel phone detection
 Compliant with FCC, China, JATE, and 31 other PTTs
 Line-in-use detection
*AT command set support
*Call progress support
*3.3 V Power
*Lead-free and RoHS-compliant packages

Applications
*Set-top boxes
*Point-of-sale
*ATM terminals
*Security systems
*Medical monitoring
*Power meters

Si3008

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DESCRIPTION
*Analog Peripherals
*Two 16-Bit ADCs
-±0.75 LSB INL; no missing codes
-Programmable throughput up to 1 Msps (each ADC)
1 external input each; programmable as two single-ended or one differential ADC
-DMA to XRAM or external memory interface
-Data-dependent windowed interrupt generator
*Three Comparators
-16 programmable hysteresis values
-Configurable to generate interrupts or reset
*Internal Voltage Reference
*Precision VDD Monitor/Brown-out Detector
*On-Chip JTAG Debug & Boundary Scan
-On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required)
-Provides breakpoints, single stepping, watchpoints, stack monitor
-Inspect/modify memory and registers
-Superior performance to emulation systems using ICE-chips, target pods, and sockets
-IEEE1149.1 compliant boundary scan
*High-Speed 8051 μC Core
-Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz system clock
-Expanded interrupt handler
*Memory
-4352 bytes data RAM
-32 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved)
-External parallel data memory interface
*Digital Peripherals
-59 port I/O; all are 5 V tolerant
-Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently
-Programmable 16-bit counter/timer array with six capture/compare modules
-5 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
-Real-time clock mode using timers or PCA
*Clock Sources
-Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
-External oscillator: Crystal, RC, C, or Clock
-Can switch between clock sources on-the-fly
*Supply Voltage: 2.7 to 3.6 V
-Typical operating current: 18 mA at 25 MHz
-Multiple power saving sleep and shutdown modes
*100-Pin TQFP
*Temperature Range: –40 to +85 °C

TAG ADC, MCU

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Description
The Si5100 is a complete low-power transceiver for high-speed serial communication systems operating between OC-48 and 2.7 Gbps.
The receive path consists of a fully-integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer.
The transmit path combines a low-jitter clock multiplier unit (CMU) with a 16:1 serializer.
The CMU uses Silicon Laboratories’ DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components.
To simplify BER optimization in long-haul applications, programmable slicing and sample phase
adjustment are supported.
The Si5100 operates from a single 1.8 V supply over the industrial temperature range (–20 to 85 °C).

Features
Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX
* Data rates supported: OC-48/STM-16 through 2.7 Gbps FEC
* Low-power operation 1.2 W (typ)
* DSPLL™ based clock multiplier unit w/ selectable loop filter bandwidths
* Integrated limiting amplifier
* Loss-of-signal (LOS) alarm
* Diagnostic and line loopbacks
* SONET-compliant loop timed operation
* Programmable slicing level and sample phase adjustment
* LVDS/LVPECL compatible interface
* Single supply 1.8 V operation
* 15 x 15 mm BGA package

Applications
* SONET/SDH transmission systems
* Optical transceiver modules
* SONET/SDH test equipment

SI5100-F-BC

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