GENERAL DESCRIPTION
The K4M56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

FEATURES
*1.8V power supply.
*LVCMOS compatible with multiplexed address.
*Four banks operation.
*MRS cycle with address key programs.
-CAS latency (1, 2 & 3).
-Burst length (1, 2, 4, 8 & Full page).
-Burst type (Sequential & Interleave).
*EMRS cycle with address key programs.
*All inputs are sampled at the positive going edge of the system clock.
*Burst read single-bit write operation.
*Special Function Support.
-PASR (Partial Array Self Refresh).
-Internal TCSR (Temperature Compensated Self Refresh)
-DS (Driver Strength)
-DPD (Deep Power Down)
*DQM for masking.
*Auto refresh.
*64ms refresh period (8K cycle)
*Commercial Temperature Operation (-25°C ~ 70°C).
*Extended Temperature Operation (-25°C ~ 85°C).
*54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).

K4M56163PG-RE75, K4M56163PG-BE75, K4M56163PG-RG75

GENERAL DESCRIPTION
The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
*3.3V power supply
*LVTTL compatible with multiplexed address
*Dual banks operation
*MRS cycle with address key programs
-CAS Latency ( 2 & 3)
-Burst Length (1, 2, 4, 8 & full page)
-Burst Type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*Burst Read Single-bit Write operation
*DQM for masking
*Auto & self refresh
*15.6us refresh duty cycle (2K/32ms)

KM416S1120DT-G/FC, KM416S1120DT-G/F6, KM416S1120DT-G/F7

GENERAL DESCRIPTION
bw1254x is a CMOS 14bit analog-to-digital converter (ADC). It converts the analog input signal into 14bit binary digital codes at a maximum sampling rate of 10MHz.
The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current reference and voltage reference. The structure allows both differential and single-ended input.

FEATURES
*Resolution : 14bit
*Maximum Conversion Rate : 10MHz
*Package Type : 48TSSOP
*Power Supply : 3.3V
*Power Consumption : 120mW (typical)
*Reference Voltage : Internal reference or 2V, 1V (dual reference)
*Input Range : 0.5V ~ 2.5V (2.0VP-P)
*Differential Linearity Error : ±0.7 LSB
*Integral Linearity Error : ±1.5 LSB
*Signal to Noise & Distortion Ratio : 72dB
*Total Harmonic Distortion : 80dB
*Out of Range Indicator
*Digital Output : CMOS Level
*Operating Temperature Range : 0°C ~ 70°C

TYPICAL APPLICATIONS
*Imaging (Copiers, Scanners, Cameras)
*Medical Instruments
*Digital Communication Systems
*uADSL System

GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by SAMSUNG¢s advanced CMOS process technology. The family support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery backup operation with low data retention current.

FEATURES
*Process Technology: TFT
*Organization: 256Kx8
*Power Supply Voltage
-K6T2008V2A Family: 3.0V~3.6V
-K6T2008U2A Family: 2.7V~3.3V
*Low Data Retention Voltage: 2V(Min)
*Three State Outputs
*Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F 48-FBGA-6.00x7.00

K6T2008V2A-B, K6T2008U2A-B, K6T2008V2A-F, K6T2008U2A-F

GENERAL DESCRIPTION
The K4S561632C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
*JEDEC standard 3.3V power supply
*LVTTL compatible with multiplexed address
*Four banks operation
*MRS cycle with address key programs
 -CAS latency (2 & 3)
 -Burst length (1, 2, 4, 8 & Full page)
 -Burst type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock.
*Burst read single-bit write operation
*DQM for masking
*Auto & self refresh
*64ms refresh period (8K Cycle)

K4S561632C-TC/L60, K4S561632C-TC/L7C, K4S561632C-TC/L75

GENERAL DESCRIPTION
This product is SD Digital-To-Analog Converter for digital audio System (CDP). The product contains Serial-to- Parallel Converter and Compensation Filter, Digital Volume Attenuator by the MICOM Interface, De-Emphasis Filter, FIR filter, Sinc Filter, digital sigma-delta modulator, analog postfilter, AIF (Anti-Image-Filter). The normal input and output channels provides 90dB SNR (Signal to Noise Ratio) over in band (20kHz).
The product employs the 1bit 4th-order sigma-delta architecture with 16bit resolution, over sampling of 64X. And analog postfilter with low clock sensitivity and linear phase, filters the shaping-nosie and outputs analog voltage with high resolution. An on-chip reference voltage is included to allow single supply operations.

FEATURES
* 16bit SD Digital-To-Analog Converter
* On-Chip Analog Postfilter
* Filtered Line-Level Outputs, Linear Phase Filtering
* On-Chip Voltage Reference
* 90dB SNR
* Sampling Rate 44.1kHz
* Input Rate 1Fs or 2Fs by Normal Mode/Double Mode Selection
* Zero Input Detection Mute
* On-Chip Compensation Filter
* Input Volume Attenuator by the MICOM Interface
* On-Chip De-Emphasis Filter
* On-Chip 4 times oversampling Digital Filter
* Low Clock Jitter Sensitivity
* Single 3.3V~2.5V Power Supply

APPLICATIONS
CD Player, Portable CD Player, CD-ROM, Video-CD, Mini-Disk, DVD etc

512Kx36 & 1Mx18 Synchronous Pipelined SRAM

FEATURES
• 512Kx36 or 1Mx18 Organizations.
• 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).

FUNCTION DESCRIPTION
The K7P163666A and K7P161866A are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36 bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

K7P163666A-HC33
K7P163666A-HC30
K7P163666A-HC25
K7P161866A-HC33
K7P161866A-HC30
K7P161866A-HC25

FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future frequency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus.
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
• Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data traceability.
• Single address bus.
• Byte write function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm & Lead Free

GENERAL DESCRIPTION
 The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M.

 Address, data inputs, and all control signals are synchronized to the input clock (K or K).
Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K).
Read data are referenced to echo clock (CQ or CQ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fixed to 4-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.

 Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

 The K7I643684M and K7I641884M are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.


K7I641884M
K7I643684M-F(E)C(I)30
K7I643684M-F(E)C(I)25
K7I643684M-FC(I)20
K7I643684M-FC(I)16
K7I641884M-F(E)C(I)30
K7I641884M-F(E)C(I)25
K7I641884M-FC(I)20
K7I641884M-FC(I)16

RGB ENCODER
The KA2195D is a monolithic integrated circuit designed for RGB encoder of video system. This device contains matrix of R-Y/B-Y, modulator, pulse generator, regulator and built in BPF of chroma and delay line of luminance. The KA2195D is suitable for video equipment

FUNCTION
· Regulator
· Mixer of R-Y, B-Y
· Modulator
· Pulse generator
· Audio buffer
· X-tal oscillator
· Clamp circuit
· BPF & D.L circuit

FEATURE
· Lower operating voitage:Vcc= 5V
· Stabilized bias condition in regulator
· Available only NTSC system
· Included 75 ohm driver (RGB Output, composite video output, composite sync. output)
· Sub-carrier frequency using X-tal and available external input
· Include BPF & delay line :Minimized external components
· Audio buffer circuit
· R-Y, B-Y modulator

FEATURES
• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin

K4D263238A-GC33
K4D263238A-GC36
K4D263238A-GC40
K4D263238A-GC45
K4D263238A-GC50