Description
The SSTX4915 is a low power ASK transmitter IC intended for applications in the North American and European VHF/UHF bands. The integrated voltage-controlled oscillator (VCO), phase/frequency detector, prescaler, and reference oscillator require only the addition of an external crystal to provide a complete phase-locked loop (PLL). In addition to the standard power-down mode, the chip also includes an automatic lock-detect feature that disables the transmitter output when the PLL is out-of-lock.

Features
*Output frequency range: 100 – 960 MHz
*Supply voltage range: 2.2 – 3.6 V
*Low current consumption with power down capability
*On-chip VCO with integrated PLL (÷ 64/128) dual modulus prescaler
*Out-of-lock inhibit circuit
*SSOP-16 package (0.64 mm pitch)

Applications
*Wireless mouse
*Car alarm and home security systems
*Remote control systems

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PRODUCT DESCRIPTION
The SST12LP07 is a versatile power amplifier based on the highly-reliable InGaP/GaAs HBT technology.
The SST12LP07 can be easily configured for high-power applications with good power-added efficiency while operating over the 2.4- 2.5 GHz frequency band. This device typically provides 29 dB gain with 22% power-added efficiency @ POUT = 22 dBm for 802.11g and 21% poweradded efficiency @ POUT = 22 dBm for 802.11b.
The SST12LP07 has excellent linearity, typically ~2.5% added EVM at 19 dBm output power which is essential for 54 Mbps 802.11g/n operation while meeting 802.11g spectrum mask at 22 dBm. The SST12LP07 can also be configured for high-efficiency operation, typically 17 dBm linear 54 Mbps 802.11g output power at 85 mA total power consumption. High-efficiency operation is desirable in embedded applications such as in hand-held units.
The SST12LP07 also features easy board-level usage along with high-speed power-up/down control through a single combined reference voltage pin. Ultra-low reference current (total IREF ~2 mA) makes the SST12LP07 controllable by an on/off switching signal directly from the baseband chip. These features coupled with low operating current make the SST12LP07 ideal for the final stage power amplification in battery-powered 802.11g/b WLAN transmitter applications.
The SST12LP07 has an excellent on-chip, single-ended power detector, which features wide-range (~20 dB) with dB-wise linearization and high stability over temperature (<+/-0.3 dB 0°C to +85°C), frequency (<+/-0.3 dB across Channels 1 through 14), and output load (<+/-0.4 dB
with 2:1 output VSWR all phases). The excellent onchip power detector provides a reliable solution to board-level power control.
The SST12LP07 is offered in a 16-contact VQFN package. See Figure 2 for pin assignments and Table 1 for pin descriptions.

FEATURES
*High Gain:
-Typically 29 dB gain across 2.4–2.5 GHz over temperature 0°C to +85°C
*High linear output power:
->26 dBm P1dB
--Please refer to “Absolute Maximum Stress Ratings” on page 4
-Meets 802.11g OFDM ACPR requirement up to 22 dBm
-~2.5% added EVM up to 19 dBm for 54 Mbps 802.11g signal
-Meets 802.11b ACPR requirement up to 22 dBm
*High power-added efficiency/Low operating current for both 802.11g/b applications
-~22%/220 mA @ POUT = 22 dBm for 802.11g
-~21%/230 mA @ POUT = 22 dBm for 802.11b
*Single-pin low IREF power-up/down control
-IREF <2 mA
*Low idle current
-~70 mA ICQ
*High-speed power-up/down
-Turn on/off time (10%- 90%) <100 ns
-Typical power-up/down delay with driver delay included <200 ns
*High temperature stability
-~1 dB gain/power variation between 0°C to +85°C
*Low shut-down current (< 0.1 μA)
*Excellent On-chip power detection
-<+/- 0.3dB variation between 0°C to +85°C
-<+/- 0.4dB variation with 2:1 VSWR mismatch
-<+/- 0.3dB variation Ch1 through Ch14
*20 dB dynamic range on-chip power detection
*Simple input/output matching

APPLICATIONS
*WLAN (IEEE 802.11g/b)
*Home RF
*Cordless phones
*2.4 GHz ISM wireless equipment
*Packages available
-16-contact VQFN – 3mm x 3mm
*All non-Pb (lead-free) devices are RoHS compliant

SST12LP07-QVCE-K, SST12LP07-QVCE

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PRODUCT DESCRIPTION
The SST12LP10 is a high-performance power amplifier based on the highly-reliable InGaP/GaAs HBT technology.
The SST12LP10 can be easily configured for high-power, high-efficiency applications with superb power-added efficiency while operating over the 2.4~2.5 GHz frequency band. It provides over 26 dB gain with 19% power-added efficiency @ POUT = 20 dBm for 802.11g and 30% poweradded efficiency @ POUT = 24 dBm for 802.11b.
The SST12LP10 has excellent linearity (over 20 dBm linear output with total system EVM<5%) which is essential for 54 Mbps 802.11g operation.
The power amplifier IC also features easy board-level usage along with high-speed power-up/down control and ultra-low reference current (~3 mA). These features coupled with low operating current make the SST12LP10 ideal for the final stage power amplification in battery-powered 802.11g/b WLAN transmitter applications.
The SST12LP10 is offered in 16-contact VQFN package. See Figure 1 for pin assignments and Table 1 for pin descriptions.

FEATURES
*High Gain:
–>26 dB gain across 2.4~2.5 GHz over temperature 0°C to +80°C
*High linear output power:
–~27 dBm P1dB
–Meets 802.11g OFDM ACPR requirement up to 23 dBm
–Over 20 dBm linear output with total system EVM<5% for 54 Mbps 802.11g signal
–Meets 802.11b ACPR requirement up to 24 dBm
*High power-added efficiency/Low operating current for both 802.11g/b applications
–~19% @ POUT = 20 dBm for 802.11g
–~30% @ POUT = 24 dBm for 802.11b
*Ultra-low Reference Current
–~3 mA Total IREF
*Low idle current
–~60 mA ICQ
*High-speed power-up/down
–Turn on/off time (10%~90%) <100 ns
–Typical power-up/down delay with driver delay included <200 ns
*High temperature stability
–~1 dB gain/power variation between 0°C to +80°C
*Low shut-down current (< 0.1 μA)
*Simple input/output matching
*Packages available
–16-contact VQFN (3mm x 3mm)
–Non-Pb (lead-free) packages available

APPLICATIONS:
*WLAN (IEEE 802.11g/b)
*Home RF
*Cordless phones
*2.4 GHz ISM wireless equipment

SST12LP10-QVC, SST12LP10-QVCE, SST12LP10-QVC-K, SST12LP10-QVCE-K

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PRODUCT DESCRIPTION
The SST12LN01 is a cost effective Low Noise Amplifier LNA) which does not require external RF-matching components on PCB applications. This device is based on the 0.5μm GaAs PHEMT technology, and complies with 802.11 b/g applications.
SST12LN01 provides high-performance, low-noise, and mild-gain operations within the 2.4–2.5 GHz frequency band. Across this frequency band, this device typically provides 12-13 dB gain.
This LNA cell is equipped with a self DC-biasing scheme, which helps keep the DC consumption very low during operation. A pair of singled-ended, input and output ports is assigned to the LNA cell with a 50 RF match.
The SST12LN01 is offered in a 6-contact UQFN package. See Figure 2 for pin assignments and Table 1 for pin descriptions.

FEATURES
*Suitable Gain:
–Typically 12-13 dB gain across 2.4–2.5 GHz
*Low Noise Figure:
–1.2-1.5 dB across 2.4–2.5 GHz
*IIP3:
–3 dBm across 2.4–2.5 GHz
*Low Current Consumption
–12 mA across 2.4–2.5 GHz
*50Ω Input/Output Matched
*Packages available
–16-contact UQFN – 3 mm x 1.6 mm
*All non-Pb (lead-free) devices are RoHS compliant

APPLICATIONS
*WLAN
*Bluetooth
*Wireless Network

SST12LN01-QU6F-K, SST12LN01-QU6F

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PRODUCT DESCRIPTION
The SST39WF400A device is a 256K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF400A writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories.
Featuring high-performance Word-Program, the SST39WF400A device provides a typical Word-Program time of 28 μsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39WF400A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, it significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF400A is offered in both a 48-ball TFBGA package and 48-ball Micro-Packages. See Figures 1 and 2 for pin assignments.

FEATURES
*Organized as 256K x16
*Single Voltage Read and Write Operations
– 1.65-1.95V
*Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
*Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 μA (typical)
*Sector-Erase Capability
– Uniform 2 KWord sectors
*Block-Erase Capability
– Uniform 32 KWord blocks
*Fast Read Access Time
– 90 ns
– 100 ns
*Latched Address and Data
*Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 μs (typical)
*Automatic Write Timing
– Internal VPP Generation
*End-of-Write Detection
– Toggle Bit
– Data# Polling
*CMOS I/O Compatibility
*JEDEC Standard
– Flash EEPROM Pinouts and command sets
*Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-bump XFLGA (4mm x 6mm) Micro-Package

SST39WF400A-90-4C-B3K, SST39WF400A-90-4C-B3KE

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PRODUCT DESCRIPTION
The SST89E5xRD2/RD and SST89V5xRD2/RD are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The devices come with 16/24/40 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 8/16/32 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary block can be mapped to the lowest location of the 8/16/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory.
In addition to the 16/24/40 KByte of EEPROM program memory on-chip, the devices can address up to 64 KByte of external program memory. In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.
The flash memory blocks can be programed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST’s devices. During poweron reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation. The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The devices are pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the user’s reference and convenience only; SST does not guarantee its functionality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.

FEATURES
*8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
*SST89E5xRD2 Operation
– 0 to 40 MHz at 5V
*SST89V5xRD2 Operation
– 0 to 33 MHz at 3V
*1 KByte Internal RAM
*Dual Block SuperFlash EEPROM
– 8/16/32 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
*Support External Address Range up to 64 KByte of Program and Data Memory
*Three High-Current Drive Ports (16 mA each)
*Three 16-bit Timers/Counters
*Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
*Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
*Programmable Watchdog Timer (WDT)
*Programmable Counter Array (PCA)
*Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port
*Second DPTR register
*Low EMI Mode (Inhibit ALE)
*SPI Serial Interface
*Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle.
*TTL- and CMOS-Compatible Logic Levels
*Brown-out Detection
*Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
*Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
*Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
*All non-Pb (lead-free) devices are RoHS compliant

SST89E52RD-40-C-PI, SST89E52RD-40-C-PIE, SST89E52RD-40-I-PI, SST89E52RD-40-I-PIE, SST89V52RD-33-C-PI, SST89V52RD-33-C-PIE, SST89V52RD-33-I-PI, SST89V52RD-33-I-PIE, SST89E54RD-40-C-PI, SST89E54RD-40-C-PIE, SST89E54RD-40-I-PI, SST89E54RD-40-I-PIE, SST89V54RD-33-C-PI, SST89V54RD-33-C-PIE, SST89V54RD-33-C-QIF, SST89V54RD-33-I-PI, SST89V54RD-33-I-PIE, SST89V54RD-33-I-QIF, SST89E58RD-40-C-PI, SST89E58RD-40-C-PIE, SST89E58RD-40-I-PI, SST89E58RD-40-I-PIE, SST89V58RD-33-C-PI, SST89V58RD-33-C-PIE, SST89V58RD-33-I-PI, SST89V58RD-33-I-PIE

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PRODUCT DESCRIPTION
The SST89E564RD, SST89V564RD, SST89E554RC, and SST89V554RC are members of the FlashFlex51 family of 8- bit microcontroller products designed and manufactured with the state-of-the-art SuperFlash CMOS semiconductor process technology.
The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The device comes with 72/40 KByte of on-chip flash EEPROM program memory using SST’s patented and proprietary CMOS SuperFlash EEPROM technology with the SST’s field- enhancing, tunneling injector, split-gate memory cells.
The SuperFlash memory is partitioned into 2 independent program memory blocks.
The primary Super- Flash Block 0 occupies 64/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 8 KByte of internal program memory space.
The 8-KByte secondary SuperFlash block can be mapped to the lowest location of the 64/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST’s device.
During the power-on reset, the device can be configured as a slave to an external host for source code storage or as a master to an external host for an in-application programming (IAP) operation.
The device is designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility.
The device is pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating
via the IAP operation.
An example bootstrap loader is available for the user’s reference and convenience only.
SST does not guarantee the functionality or the usefulness of the sample bootstrap loader.
Chip-Erase operations will erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64 KByte of external program memory.
In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.
SST’s highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs.
These advantages translate into significant cost and reliability benefits for our customers.

FEATURES
*8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory
-Fully Software Compatible
-Development Toolset Compatible
-Pin-For-Pin Package Compatible
*SST89E564RD/SST89E554RC Operation
-0 to 40 MHz at 5V
*SST89V564RD/SST89V554RC Operation
-0 to 33 MHz at 3V
*Total 1 KByte Internal RAM (256 Byte + 768 Byte)
*Dual Block SuperFlash EEPROM
-SST89E564RD/SST89V564RD: 64 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
-SST89E554RC/SST89V554RC: 32 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
-Individual Block Security Lock with SoftLock
-Concurrent Operation during In-Application Programming (IAP)
-Memory Overlay for Interrupt Support during IAP
*Support External Address Range up to 64 KByte of Program and Data Memory
*Three High-Current Port 1 pins (16 mA each)
*Three 16-bit Timers/Counters
*Full-Duplex, Enhanced UART
-Framing error detection
-Automatic address recognition
*Eight Interrupt Sources at 4 Priority Levels
*Programmable Watchdog Timer (WDT)
*Programmable Counter Array (PCA)
*Four 8-bit I/O Ports (32 I/O Pins)
*Second DPTR register
*Low EMI Mode (Inhibit ALE)
*SPI Serial Interface
*Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
*TTL- and CMOS-Compatible Logic Levels
*Brown-out Detection
*Low Power Modes
-Power-down Mode with External Interrupt Wake-up
-Idle Mode
*PDIP-40, PLCC-44 and TQFP-44 Packages
*Temperature Ranges:
-Commercial (0°C to +70°C)
-Industrial (-40°C to +85°C)

SST89V564RD
SST89V564RD
TAG Flash, MCU

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PRODUCT DESCRIPTION
The SST39WF800A device is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
The SST39WF800A writes (Program or Erase) with a 1.65-1.95V power supply.
This device conforms to JEDEC standard pin assignments for x16 memories.
Featuring high-performance Word-Program, the SST39WF800A device provides a typical Word-Program time of 28 μsec.
The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation.
To protect against inadvertent writes, it has on-chip hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles.
Data retention is rated at greater than 100 years.
The SST39WF800A device is suited for applications that require convenient and economical updating of program, configuration, or data memory.
For all system applications, it significantly improves performance and reliability, while lowering power consumption.
It inherently uses less energy during Erase and Program than alternative flash technologies.
When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.
These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred.
Therefore the system software or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF800A is offered in a 48-ball TFBGA package and a 48-ball Micro- Package.

FEATURES
* Organized as 512K x16
* Single Voltage Read and Write Operations
- 1.65-1.95V
* Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
* Low Power Consumption (typical values at 5 MHz)
- Active Current: 5 mA (typical)
- Standby Current: 5 μA (typical)
* Sector-Erase Capability
- Uniform 2 KWord sectors
* Block-Erase Capability
- Uniform 32 KWord blocks
* Fast Read Access Time
- 90 ns
* Latched Address and Data
* Fast Erase and Word-Program
- Sector-Erase Time: 36 ms (typical)
- Block-Erase Time: 36 ms (typical)
- Chip-Erase Time: 140 ms (typical)
- Word-Program Time: 28 μs (typical)
* Automatic Write Timing
- Internal VPP Generation
* End-of-Write Detection
- Toggle Bit
- Data# Polling
* CMOS I/O Compatibility
* JEDEC Standard
- Flash EEPROM Pinouts and command sets
* Packages Available
- 48-ball TFBGA (6mm x 8mm)
- 48-ball WFBGA (4mm x 6mm) Micro-Package
- 48-ball WFBGA (5mm x 6mm) Micro-Package
- 48-ball XFLGA (5mm x 6mm) Micro-Package
* All non-Pb (lead-free) devices are RoHS compliant

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PRODUCT DESCRIPTION
 The SST89E5xRD2/RD and SST89V5xRD2/RD are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology.
The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers.
The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The devices come with 16/24/40 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks.
The primary Block 0 occupies 8/16/32 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.
The 8-KByte secondary block can be mapped to the lowest location of the 8/16/32 KByte address space; it can also be hidden from the program counter and used as an independent
EEPROM-like data memory.
In addition to the 16/24/40 KByte of EEPROM program memory on-chip, the devices can address up to 64 KByte of external program memory.
In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST’s devices.
During poweron reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation.
The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility.
The devices are pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation.
The sample bootstrap loader is available for the user’s reference and convenience only; SST does not guarantee its functionality or usefulness.
Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.

FEATURES
* 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory
- Fully Software Compatible
- Development Toolset Compatible
- Pin-For-Pin Package Compatible
* SST89E5xRD2 Operation
- 0 to 40 MHz at 5V
* SST89V5xRD2 Operation
- 0 to 33 MHz at 3V
* 1 KByte Internal RAM
* Dual Block SuperFlash EEPROM
- 8/16/32 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
- Individual Block Security Lock with SoftLock
- Concurrent Operation during In-Application Programming (IAP)
- Memory Overlay for Interrupt Support during IAP
* Support External Address Range up to 64 KByte of Program and Data Memory
* Three High-Current Drive Ports (16 mA each)
* Three 16-bit Timers/Counters
* Full-Duplex, Enhanced UART
- Framing Error Detection
- Automatic Address Recognition
* Ten Interrupt Sources at 4 Priority Levels
- Four External Interrupt Inputs
* Programmable Watchdog Timer (WDT)
* Programmable Counter Array (PCA)
* Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port
* Second DPTR register
* Low EMI Mode (Inhibit ALE)
* SPI Serial Interface
* Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle.
* TTL- and CMOS-Compatible Logic Levels
* Brown-out Detection
* Low Power Modes
- Power-down Mode with External Interrupt Wake-up
- Idle Mode
* Temperature Ranges:
- Commercial (0°C to +70°C)
- Industrial (-40°C to +85°C)
* Packages Available
- 40-contact WQFN (Port 4 feature not available)
- 44-lead PLCC
- 40-pin PDIP (Port 4 feature not available)
- 44-lead TQFP
* All non-Pb (lead-free) devices are RoHS compliant

SST89E52RD2/RD
SST89E54RD2/RD
SST89E58RD2/RD
SST89V52RD2/RD
SST89V54RD2/RD
SST89V58RD2/RD

TAG flex, MCU

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FEATURES
• 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89E5xRD2 Operation
– 0 to 40 MHz at 5V
• SST89V5xRD2 Operation
– 0 to 33 MHz at 3V
• 1 KByte Internal RAM
• Dual Block SuperFlash EEPROM
– 8/16/32 KByte primary block + 8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
• Support External Address Range up to 64 KByte of Program and Data Memory
• Three High-Current Drive Ports (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION
The SST89E5xRD2/RD and SST89V5xRD2/RD are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The devices come with 16/24/40 KByte of on-chip flash EEPROM program memory which is partitioned into independent program memory blocks. The primary Block occupies 8/16/32 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary block can be mapped to the lowest location of the 8/16/32 KByte address space; it can also be hidden from the program counter and used as an independent
EEPROM-like data memory.
In addition to the 16/24/40 KByte of EEPROM program memory on-chip, the devices can address up to 64 KByte of external program memory. In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST’s devices. During poweron reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation.
The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The devices are pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the user’s reference and convenience only; SST does not guarantee its functionality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.

SST89E54RD2
SST89E58RD2
TAG MCU

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