GENERAL DESCRIPTION
The SAA7345 incorporates the CD signal processing functions of decoding and digital filtering. The device is equipped with on-board SRAM and includes additional features to reduce the processing required in the analog domain.
Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
FEATURES
*Integrated data slicer and clock regenerator
*Digital Phase-Locked Loop (PLL)
*Demodulator and Eight-to-Fourteen Modulation (EFM) decoding
*Subcoding microcontroller serial interface
*Integrated programmable motor speed control
*Error correction and concealment functions
*Embedded Static Random Access Memory (SRAM) for de-interleave and First-In First-Out (FIFO)
*FIFO overflow concealment for rotational shock resistance
*Digital audio interface [European Broadcasting Union (EBU)]
*2 to 4 times oversampling integrated digital filter
*Audio data peak level detection
*Versatile audio data serial interface
*Digital de-emphasis filter
*Kill interface for Digital-to-Analog Converter (DAC) deactivation during digital silence
*Double speed mode
*Compact Disc Read Only Memory (CD-ROM) modes
*A single speed only version is available (SAA7345GP/SS).
SAA7345GP
General description
The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
*Wide supply voltage range from 0.8 V to 3.6 V
*High noise immunity
*Complies with JEDEC standards:
-JESD8-12 (0.8 V to 1.3 V)
-JESD8-11 (0.9 V to 1.65 V)
-JESD8-7 (1.2 V to 1.95 V)
-JESD8-5 (1.8 V to 2.7 V)
-JESD8-B (2.7 V to 3.6 V)
*ESD protection:
-HBM JESD22-A114-D Class 3A exceeds 5000 V
-MM JESD22-A115-A exceeds 200 V
-CDM JESD22-C101-C exceeds 1000 V
*Low static power consumption; ICC = 0.9 mA (maximum)
*Latch-up performance exceeds 100 mA per JESD 78 Class II
*Inputs accept voltages up to 3.6 V
*Low noise overshoot and undershoot < 10 % of VCC
*IOFF circuitry provides partial Power-down mode operation
*Multiple package options
*Specified from -40 °C to +85 °C and -40 °C to +125 °C
74AUP1G74DC, 74AUP1G74GT, 74AUP1G74GM
GENERAL DESCRIPTION
The TDA9952 is a 10-bit analog-to-digital interface for CCD cameras. The device consists of a Correlated Double Sampling (CDS) circuit, a digitally Programmable Gain Amplifier (PGA), a black level clamp and a 10-bit Analog-to-Digital Converter (ADC).
An internal CDS input buffer is incorporated in order to avoid using an external buffer that would consume more power and therefore optimizing the application for low noise, low power working.
The PGA gain, the ADC clamp level and other settings are controlled via a 3-wire serial digital interface.
An additional DAC is provided for system controls.
The TDA9952 operates from a single 3 V power supply (2.7 V minimum) and dissipates 135 mW (typical value).
FEATURES
*Sample rate = 25 Msps;10-bit resolution
*Single 3.0 V supply operation (2.2 to 3.6 V operation for the digital outputs)
*Low power consumption: only 115 mW at 2.7 V
*Power consumption in standby mode: 4.5 mW (typical value)
*Programmable gain amplifier : gain range = 36 dB in 0.1 dB steps
*Correlated double sampling
*Internal input buffer for the correlated double sampling
*Fully programmable via a 3-wire serial interface
*8-bit DAC included for external analog settings
*TTL-compatible inputs and CMOS-compatible outputs.
APPLICATIONS
*Video camcorders
*Digital still cameras
*PC-cameras.
TDA9952HL, TDA9952HN
General description
Single high-speed switching diode, fabricated in planar technology, and encapsulated in a small hermetically sealed glass SOD80C SMD package.
Features
*Small hermetically sealed glass SMD package
*High switching speed: £ 4 ns
*Continuous reverse voltage: £ 75 V
*Repetitive peak reverse voltage: £ 100 V
*Repetitive peak forward current: £ 450 mA
Applications
*High-speed switching
*Inverse-polarity protection
General Description
The SL RC400 is member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz.
This new reader IC family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless communication methods and protocols at 13.56 MHz.
The SL RC400 supports all layers of I*CODE1 and ISO 15693.
The internal transmitter part is able to drive an antenna designed for proximity operating distance (up to 100 mm) directly without additional active circuitry.
The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from I*CODE1 and ISO 15693 compatible transponders.
The digital part handles I*CODE1 and ISO 15693 framing and error detection (CRC).
A comfortable parallel interface which can be directly connected to any 8-bit μ-Processor gives high flexibility for the reader/terminal design.
Features
* Highly integrated analog circuitry to demodulate and decode label response
* Buffered output drivers to connect an antenna with minimum number of external components
* Proximity operating distance (up to 100 mm)
* Supports I*CODE1 and ISO 15693
* Parallel μ-Processor interface with internal address latch and IRQ line
* Flexible interrupt handling
* Automatic detection of parallel μC interface type
* Comfortable 64 byte send and receive FIFO-buffer
* Hard reset with low power function
* Power down mode per software
* Programmable timer
* Unique serial number
* User programmable start-up configuration
* Bit- and byte-oriented framing
* Independent power supply pins for digital, analog and transmitter part
* Internal oscillator buffer to connect 13.56 MHz quartz, optimised for low phase jitter
* Clock frequency filtering
* 3.3 V operation for transmitter (antenna driver) in short range applications
SLRC40001T
Features
· Extended system operating range due to powerful AM/PM demodulation technique
· Ideally suited for "Intelligent Antenna" and "Active Antenna" architectures
· High antenna drive capabilities, CW: 200mAp
· Low antenna driver output resistance, 3.5 W
· Excellent receiver sensitivity, 2mVpp
· Large receiver dynamic range
· Programmable clock divider, modulator, receiver gain and filter characteristics
· Fast "read after write" receiver settling characteristics
· On-chip receive EMI filter
· Antenna failure mode detection
· Few external components
· Operating supply voltage: 4.5 to 5.5 V
· Power down mode: 7mA @ 5.5 V
· 14-pin SO package
General Description
The PCF7991 is a highly integrated and powerful advanced basestation IC, ABIC, ideally suited for vehicle immobilisation applications. The device incorporates all necessary functions to facilitate reading and writing of transponders.
The ABIC, PCF7991 employs a unique AM/PM demodulation technique that extends the system operating range compared with simple envelope detection. Optimised to operate with the Philips transponder family (PCF79xx), the ABIC can be used in combination with commonly available transponder that employ ASK modulation. ASK modulation and receive characteristics are widely programmable for powerful system adaptation. The ABIC fits "Intelligent Antenna" as well
as "Active Antenna" applications.
The carrier frequency can be derived from an on-chip oscillator or an external clock source. A wide range of clock frequencies can be applied due to the programmable on-chip clock divider circuitry.
The device enables system diagnostic functions by antenna fail detection features.
Communication with the device and the transponder is provided via the serial microcontroller interface.
Employing CMOS technology, the device features low power operation and supports Idle and Powerdown modes.
General description
The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G00 provides the single 2-input NAND function.
Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
+ JESD8-12 (0.8 V to 1.3 V)
+ JESD8-11 (0.9 V to 1.65 V)
+ JESD8-7 (1.2 V to 1.95 V)
+ JESD8-5 (1.8 V to 2.7 V)
+ JESD8-B (2.7 V to 3.6 V)
* ESD protection:
+ HBM JESD22-A114-C Class 3A. Exceeds 5000 V
+ MM JESD22-A115-A exceeds 200 V
+ CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C
74AUP1G00GW
74AUP1G00GM
74AUP1G00GF
FEATURES
• Metastable immune characteristics
• Pin compatible with 74F74 and 74F5074
• Typical fMAX = 200 MHz
• Output skew guaranteed less than 2.0 ns
• High source current (IOH = 15 mA) ideal for clock driver applications
• Output capability: +20 mA / –15 mA
• Latch-up protection exceeds 50 0mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active-LOW inputs and operate independently of the clock (CPn) input. Data must be stable just one set-up time prior to the LOW-to-HIGH transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a metastable state due to set-up and hold time violations. If set-up time and hold time are violated the propagation delays may be extended beyond the specifications, but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are:
t @ 94 ps and To @ 1.3 × 107 sec
where t represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
74ABT5074D
74ABT5074DB
74ABT5074PW
DESCRIPTION
The 87C51FA and 87C51FB Single-Chip 8-Bit Microcontrollers are manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. The 87C51FA/FB has the same instruction set as the 80C51.
This device provides architectural enhancements that make it applicable in a variety of applications for general control systems.
The 87C51FA contains 8k × 8 memory, and the 87C51FB contains 16k × 8 memory. They both contain a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a Programmable Counter Array (PCA), a multi-source, two-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C51FA/FB can be expanded using standard TTL compatible memories and logic.
Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.
See 83C51FA/83C51FB/83C51FC/80C51FA datasheet for ROM and ROMless devices.
FEATURES
• 80C51 central processing unit
• 87C51FA: 8k × 8 EPROM 87C51FB: 16k × 8 EPROM
– expandable externally to 64k bytes
– Quick Pulse programming algorithm
– Two level program security system
• 256 × 8 RAM, expandable externally to 64k bytes
• Three 16-bit timer/counters
– T2 is an up/down counter
• Programmable Counter Array (PCA)
– High speed output
– Capture/compare
– Pulse Width Modulator
– Watchdog Timer
• Four 8-bit I/O ports
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
• Power control modes
– Idle mode
– Power-down mode
• Once (On Circuit Emulation) Mode
• Five package styles
• OTP package available
87C51FB
General description
The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger actio*at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumptio*across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-dow*applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device whe*it is powered down.
The 74AUP1G04 provides the single inverting buffer.
Features
*Wide supply voltage range from 0.8 V to 3.6 V
*High noise immunity
*Complies with JEDEC standards:
*JESD8-12 (0.8 V to 1.3 V)
*JESD8-11 (0.9 V to 1.65 V)
*JESD8-7 (1.2 V to 1.95 V)
*JESD8-5 (1.8 V to 2.7 V)
*JESD8-B (2.7 V to 3.6 V)
*ESD protection:
*HBM JESD22-A114-C Class 3A. Exceeds 5000 V
*MM JESD22-A115-A exceeds 200 V
*CDM JESD22-C101-C exceeds 1000 V
*Low static power consumption; ICC = 0.9 mA (maximum)
*Latch-up performance exceeds 100 mA per JESD 78 Class II
*Inputs accept voltages up to 3.6 V
*Low noise overshoot and undershoot < 10 % of VCC
*IOFF circuitry provides partial Power-dow*mode operation
*Multiple package options
*Specified from -40 °C to +85 °C and -40 °C to +125 °C
74AUP1G04GW
74AUP1G04GM
74AUP1G04GF
