Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features
*1 Mbit of Flash memory
*Page Program (up to 256 bytes) in 1.4 ms (typical)
*Sector Erase (256 Kbit) in 0.65 s (typical)
*Bulk Erase (1 Mbit) in 1.7 s (typical)
*2.3 to 3.6 V single supply voltage
*SPI bus compatible serial interface
*50 MHz Clock rate (maximum)
*Deep Power-down mode 1 μA (typical)
*Electronic signatures
–JEDEC standard two-byte signature (2011h)
–RES instruction, one-byte signature (10h), for backward compatibility
*More than 20 years’ data retention
*Packages
–ECOPACK® (RoHS compliant)

M25P10-AVMN6TP/X, M25P10-AVMP6TP/X, M25P10-AVMB6TP/X

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Description
The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD power supply.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with ECC on). The device also has hardware security features; a write protect pin is available to give hardware protection against Program and Erase operations.
The devices feature an open-drain, ready/busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable “Don’t Care” feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the Read operation.
There is the option of a unique identifier (serial number), which allows the NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm) packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the category of second level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label.
The devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.

Features
*High density multilevel cell (MLC) Flash memory
-Up to 16 Gbit memory array
-Up to 512 Mbit spare area
-Cost-effective solutions for mass storage applications
*NAND interface
-x 8 bus width
-Multiplexed address/data
*Supply voltage: VDD = 2.7 to 3.6 V
*Page size: (2048 + 64 spare) bytes
*Block size: (256K + 8K spare) bytes
*Multiplane architecture
-Array split into two independent planes
-Program/erase operations can be performed on both planes at the same time
*Page read/program
-Random access: 60 μs (max)
-Sequential access: 25 ns (min)
-Page program operation time: 800 μs (typ)
*Multipage program time (2 pages): 800 μs (typ)
*Fast block erase
-Block erase time: 2.5 ms (typ)
*Multiblock erase time (2 blocks): 2.5 ms (typ)
*Status register
*Electronic signature
*Serial number option
*Chip enable ‘don’t care’
*Data protection
-Hardware program/erase locked during power transitions
*Development tools
-Error correction code models
-Bad block management and wear leveling algorithm
-HW simulation models
*Data integrity
-10,000 program/erase cycles (with ECC)
-10 years data retention
*ECOPACK® packages available

NAND16GW3C4A, NAND08GW3C2AN1E, NAND16GW3C2AN1E, NAND08GW3C4AN1E

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Description
The M29W800F is available as known good dice.
Numonyx defines known good dice as standard products offered as dice and tested for functionality and speed. Numonyx's known good die products are as reliable and of the same quality as products delivered in packages.
This datasheet describes the features specific to parts sold as known good dice. It should be read in conjunction with the M29W800F datasheet that detailfully describes the device operation. The M29W800F datasheet is available from the Numonyx website: www.numonyx.com.
The M29W800FB-KGD is a 8-Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a single-word basis using a 2.7 V to 3.6 V. On power-up the memory defaults to its read mode where it can be read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental program or erase commands from modifying the memory. Program and erase commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
The blocks in the memory are asymmetrically arranged. The first or last 64 Kbytes have been divided into four additional blocks. The 16-Kbyte boot block can be used for small initialization code to start the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage and the remaining 32-Kbyte is a small main block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

Features
*Supply voltage
–VCC = 2.7 V to 3.6 V for program, erase and read
*Access times: 90 ns
*Programming time
–10 μs per byte/word typical
*19 memory blocks
-1 boot block (top or bottom location)
–2 parameter and 16 main blocks
*Program/erase controller
– Embedded byte/word program algorithms
*Erase suspend and resume modes
– Read and program another block during erase suspend
*Unlock bypass program command
– Faster production/batch programming
*Temporary block unprotection mode
*Common flash interface
-64-bit security code
*Low power consumption
-Standby and automatic standby
*100,000 program/erase cycles per block
*Electronic signature
-Manufacturer code: 0020h
-Bottom device code M29W800FB: 225Bh

M29W800FB9D11

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Description
NAND08GAH0A and NAND16GAH0D are embedded Flash memory storage solutions with MultiMediaCard interface (eMMC™). The eMMC™ was developed for universal low cost data storage and communication media. They can be considered as high speed MultiMediaCards embedded in LFBGA169 12 x 16 x 1.4 mm, 0.5 mm pitch package instead of an MMC. The devices are fully compatible with MMC bus and hosts.
NAND08GAH0A and NAND16GAH0D communications are made through an advanced 13-pin bus. The bus can be either 1-bit, 4-bit, or 8-bit bus width. The devices operate in highspeed mode at clock frequencies equal or higher than 20 MHz. The communication protocol is defined as a part of this MMC standard and referred to as MultiMediaCard mode. For compatibility with existing controllers the devices may offer, in addition to the MultiMediaCard mode, an alternate communication protocol which is based on the SPI standard.
The devices are designed to cover a wide area of applications such as smart phones, cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications, Numonyx NAND08GAH0A and NAND16GAH0D support both 3 V supply voltage (VCC), and 1.8 V/3 V input/output voltage (VCCQ).
The devices have a built-in intelligent controller which manages interface protocols, data storage and retrieval, wear leveling, bad block management, garbage collection, internal ECC.
In order to meet environmental requirements, Numonyx offers the NAND08GAH0A and NAND16GAH0D in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an Numonyx trademark.

Features
*Packaged NAND Flash memory with MultiMediaCard interface
*1, 2 Gbytes of formatted data storage
*eMMC/MultiMediaCard system specification, compliant with V4.1
*Full backward compatibilty with previous MultiMediaCard system specification
*Bus mode
–High-speed MultiMediaCard protocol
–SPI protocol
–Three different data bus widths:1 bit, 4 bits, 8 bits
–Data transfer rate: up to 52 Mbyte/s
*Operating voltage range:
–VCCQ =1.8 V/3 V
–VCC = 3 V
*Supported clock frequencies: 0 to 52 MHz
*Multiple Block Read (x 8 at 52 MHz): up to 3.5 Mbyte/s
*Multiple Block Write (x 8 at 52 MHz): up to 8.5 Mbyte/s
*Power dissipation
–Standby current: down to 200 μA
–Read current: down to 30 mA
–Write current: down to 30 mA
*Error free memory access
–Internal enhanced data management algorithm (wear levelling, bad block management, garbage collection)
–Internal error correction code
*Data integrity
–Data reliability: less than 1 non-recoverable error per 1014 bits read
–Endurance: more that 2,000,000 Program/Erase cycles
*Security
–Password protection of data
–Built-in write protection (permanent or temporary)

NAND16GAH0D, NAND08GAH0AZA5E, NAND16GAH0AZA5E, NAND08GAH0DZA5E
TAG NAND

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Description
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A Write Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages:
*TSOP48 12 x 20mm
*VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch)
In order to meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
All devices have the Chip Enable Don't Care option, which allows the code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.
A Serial Number option, allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.

Features
*High density NAND Flash memories
– 512 Mbit memory array
– Cost effective solutions for mass storage applications
*NAND interface
– x 8 or x 16 bus width
– Multiplexed Address/ Data
*Supply voltage: 1.8 V, 3.0 V
*Page size
– x 8 device: (512 + 16 spare) bytes
– x 16 device: (256 + 8 spare) words
*Block size
– x 8 device: (16 K + 512 spare) bytes
– x 16 device: (8 K + 256 spare) words
*Page Read/Program
– Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
– Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
– Page Program time: 200 μs (typ)
*Copy Back Program mode
*Fast Block Erase: 2 ms (typ)
*Status Register
*Electronic signature
*Chip Enable ‘don’t care’
*Serial Number option
*Hardware Data Protection
– Program/Erase locked during Power transitions
*Data integrity
– 100,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
*ECOPACK® packages
*Development tools
– Error Correction Code models
– Bad Blocks Management and Wear Leveling algorithms
– Hardware simulation models

NAND512R4A2C, NAND512W3A2C, NAND512W4A2C

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Description
The M45PE16 is a 16Mbit (2M x 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or
Page Program instruction. The Page Write instruction consists of an integrated Page Erase
cycle followed by a Page Program cycle.
The memory is organized as 32 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or
2,097,152 Bytes.
The memory can be erased a page at a time, using the Page Erase instruction, or a sector
at a time, using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M45PE16 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.

Features
*SPI bus compatible serial interface
*50 MHz clock rate (maximum)
*16 Mbit of Page-Erasable Flash memory
*Page of 256 Bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
*Sector Erase (512 Kbit)
*Hardware Write protection of the bottom sector (64 KBytes)
*Electronic Signature
– JEDEC Standard two-Byte signature (4015h)
*2.7 to 3.6 V single supply voltage
*Deep Power-down mode 1 μA (typical)
*More than 100 000 Write cycles
*More than 20 years’ data retention
*Packages
– ECOPACK® (RoHS compliant)

M45PE16-VMW6TP, M45PE16-VMP6TP, M45PE16-VMW6P, M45PE16-VMP6P, M45PE16-VMW6TG, M45PE16-VMP6TG, M45PE16-VMW6G, M45PE16-VMP6G

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Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial paged Flash memories, respectively.
They are accessed by a high speed SPI-compatible bus.
The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction.
The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages.
Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131, 072 bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs.
The protection granularity is of 64 Kbytes (sector granularity).

Features
* 1 or 2 Mbit of page-erasable Flash memory
* 2.7 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 75 MHz clock rate (maximum)
* Page size: 256 bytes
- Page Write in 11 ms (typical)
- Page Program in 0.8 ms (typical)
- Page Erase in 10 ms (typical)
* SubSector Erase (32 Kbits)
* Sector Erase (512 Kbits)
* Bulk Erase (1 Mbit for M25PE10, 2 Mbits for M25PE20)
* Deep Power-down mode 1 μA (typical)
* Electronic signature
- JEDEC standard two-byte signature
(8012h for M25PE20, 8011h for M25PE10)
- Unique ID code (UID) with 16 bytes readonly, available upon customer request only in the T9HX process
* Software write protection on a 64-Kbyte sector basis
* More than 100 000 Write cycles
* More than 20 years data retention
* Hardware write protection of the memory area selected using the BP0 and BP1 bits
* Package
- ECOPACK® (RoHS compliant)

M25PE10
M25PE20-VMN6TP
M25PE20-VMP6TP

TAG bus, pinout

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Description
The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the page program instruction.
The memory is organized as 2 sectors, each containing 128 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.
The whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction.

Features
* 512 Kbits of flash memory
* Page program (up to 256 bytes) in 1.4 ms (typical)
* Sector erase (256 Kbits) in 0.65 s (typical)
* Bulk erase (512 Kbits) in 0.85 s (typical)
* 2.3 to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Deep power-down mode 1 μA (typical)
* Electronic signatures
- JEDEC standard two-byte signature (2010h)
- RES instruction, one-byte, signature (05h), for backward compatibility
* More than 100,000 erase/program cycles per sector
* More than 20 years data retention
* ECOPACK® packages available

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Description
 The NAND04G-B2D and NAND08G-BxC are part of the NAND Flash 2112 byte/1056 word page family of non-volatile Flash memories.
They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively.
The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each.
This multiplane architecture makes it possible to program 2 pages at a time (one in each plane),
or to erase 2 blocks at a time (one in each plane).
This feature reduces the average program and erase times by 50%.
The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture.
In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time.
In the NAND08G-B4C devices, each NAND04G-B2D die can be accessed independently using two sets of signals.
The devices operate from a 1.8 V or 3 V voltage supply.
Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or or 1056 words (1024 + 32 spare), respectively.
The address lines are multiplexed with the data input/output signals on a multiplexed x8
input/output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100 000 cycles with ECC (error correction
code) on.
To extend the lifetime of NAND Flash devices, the implementation of an ECC is strongly recommended.
A Write Protect pin is available to provide hardware protection against program and erase
operations.
The devices feature an open-drain ready/busy output that identifies if the P/E/R (program/erase/read) Controller is currently active.
The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
An embedded error detection code is automatically executed after each copy back operation: 1 error bit can be detected for every 528 bits.
With this feature it is no longer necessary, nor recommended, to use an external 2- bit ECC to detect copy back operation errors.
The devices have a cache read feature that improves the read throughput for large files.
During cache reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O buffers to be read.
The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller.
This is possible because Chip Enable transitions during the latency time do not stop the read operation.
Both the NAND04G-B2D and NAND08G-BxC support the ONFI 1.0 specification.

Features
* High density NAND Flash Memory
- Up to 8 Gbit memory array
- Cost-effective solution for mass storage applications
* NAND interface
- x8 or 16x bus width
- Multiplexed address/data
* Supply voltage: 1.8 V or 3.0 V device
* Page size
- x8 device: (2048 + 64 spare) bytes
- x16 device: (1024 + 32 spare) words
* Block size
- x8 device: (128K + 4 K spare) bytes
- x16 device: (64K + 2 K spare) words
* Multiplane architecture
- Array split into two independent planes
- Program/erase operations can be performed on both planes at the same time
* Page read/program
- Random access: 25 μs (max)
- Sequential access: 25 ns (min)
- Page program time: 200 μs (typ)
- Multiplane page program time (2 pages): 200 μs (typ)
* Copy back program with automatic error detection code (EDC)
* Cache read mode
* Fast block erase
- Block erase time: 1.5 ms (typ)
- Multiblock erase time (2 blocks): 1.5 ms (typ)
* Status Register
* Electronic signature
* Chip Enable ‘don’t care’
* Serial number option
* Data protection:
- Hardware program/erase disabled during power transitions
- Non-volatile protection option
* ONFI 1.0 compliant command set
* Data integrity
- 100 000 program/erase cycles (with ECC (error correction code))
- 10 years data retention
* ECOPACK® packages

NAND04GW4B2D
NAND08GR3B2C
NAND08GW3B2C
NAND08G-BXC
NAND04GR3B2D

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Description
 The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 8 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.

Features
* 4 Mbit of Flash memory
* 2.3 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Page Program (up to 256 bytes) in 1.5 ms (typical)
* Sector Erase (512 Kbit) in 1 s (typical)
* Bulk Erase (4 Mbit) in 4.5 s (typical)
* Deep Power-down mode 1 μA (typical)
* Hardware Write Protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2)
* Electronic signatures
– JEDEC standard two-byte signature (2013h)
– RES instruction, one-byte, signature (12h), for backward compatibility
* Packages
– ECOPACK® (RoHS compliant)

M25P40-VMN6TP/X
M25P40-VMP3G/X

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