General Description
The LP5521 is a three channel LED driver designed to produce variety of lighting effects for mobile devices. High efficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device has a program memory for creating variety of lighting sequences. When program memory has been loaded, LP5521 can operate independently without processor control.
LP5521 maintains excellent efficiency over a wide operating range by automatically selecting proper charge pump gain based on LED forward voltage requirements. LP5521 is able to automatically enter power-save mode, when LED outputs are not active and thus lowering current consumption.
Three independent LED channels have accurate programmable current sources and PWM control. Each channel has program memory for creating desired lighting sequences with PWM control.
LP5521 has a flexible digital interface. Trigger I/O and 32 kHz clock input allow synchronization between multiple devices. Interrupt output can be used to notify processor, when LED sequence has ended. LP5521 has four pin selectable I2C addresses.
This allows connecting up to four parallel devices in one I2C bus. GPO and INT pins can be used as a digital control pin for other devices.
LP5521 requires only four small and low cost ceramic capacitors.
LP5521 is available in tiny 2.1x1.7x0.6 mm microSMD-20 package and in 4.0x5.0x0.8 mm bumped LLP-24 package.
Comprehensive application tools are available, including command compiler for easy LED sequence programming.

Features
* Adaptive charge pump with 1x and 1.5x gain provides up to 95% LED drive efficiency
* Charge pump with soft start and overcurrent/short circuit protection
* Low input ripple and EMI
* Very small solution size, no inductor or resistors required
* 200 nA typical shutdown current
* Automatic power save mode
* I2C compatible interface
* Independently programmable constant current outputs with 8-bit current setting and 8-bit PWM control
* Typical LED output saturation voltage 50 mV and current matching 1%
* Three program execution engines with flexible instruction set
* Autonomous operation without external control
* Large SRAM program memory
* Two general purpose digital outputs
* microSMD-20 package, 0.4 mm pitch
* Bumped LLP-24 package, 0.5 mm pitch

Applications
* Fun / indicator lights
* LCD sub-display backlighting
* Keypad RGB backlighting and phone cosmetics
* Vibra, speakers, waveform generator

LP5521TM
LP5521TMX
LP5521YQ
LP5521YQX

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General Description
The LM2757 is a constant frequency pre-regulated switchedcapacitor charge pump that operates at 1.25 MHz to produce a low-noise regulated output voltage. The device can be configured to provide up to 100 mA at 4.1V, 110 mA at 4.5V, or 180 mA at 5V. Excellent efficiency is achieved without the use of an inductor by operating the charge pump in a gain of either
3/2 or 2 according to the input voltage and output voltage option selection.
The LM2757 presents a high impedance at the VOUT pin when shut down. This allows for use in applications that require the regulated output bus to be driven by another supply while the
LM2757 is shut down. A perfect fit for space-constrained, battery-operated applications, the LM2757 requires only 4 small, inexpensive ceramic capacitors. LM2757 is a tiny 1.2 mm X 1.6 mm 12–bump micro SMD device. Built in soft-start, over-current protection, and thermal shutdown features are also included in this device.

Features
* Inductorless solution uses only 4 small ceramic capacitors.
* True input-output and output-input disconnect.
* Up to 180 mA output current capability (5V).
* Selectable 4.1V, 4.5V or 5.0V output.
* Pre-regulation minimizes input current ripple.
* 1.24 MHz switching frequency for a low-noise, low-ripple output voltage.
* Efficient dual gain converter (2X, 3/2X).
* Integrated Over Current Protection.
* Integrated Thermal Shutdown Protection.
* Tiny 1.2 mm X 1.6 mm X 0.4 mm pitch, 12–bump micro SMD package.

Applications
* Keypad LED Drive
* USB/USB-OTG Power
* Cellular Phone SIM cards
* Audio amplifier power supplies
* Low-current Camera Flash
* General Purpose Li-Ion-to-5V Conversion
* Supercapacitor Charger


LM2757TM
LM2757TMX

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General Description
The COP8SBE9/SCE9/SDE9 Flash microcontrollers are highly integrated COP8™ Feature core devices, with 8k Flash memory and advanced features including Virtual EEPROM, High Speed Timers, USART, and Brownout Reset.
This single-chip CMOS device is suited for applications requiring a full featured, in-system reprogrammable controller with large memory and low EMI. The same device is used for
development, pre-production and volume production with a range of COP8 software and hardware development tools.

Features
KEY FEATURES
* 8k bytes Flash Program Memory with Security Feature
* Virtual EEPROM usi*g Flash Program Memory
* 256byte volatile RAM
* USART with o*chip baud ge*erator
* 2.7V – 5.5V I*-System Programmability of Flash
* High e*dura*ce -100k Read/Write Cycles
* Superior Data Rete*tio* - 100 years
* Dual Clock Operatio* with HALT/IDLE Power Save Modes
* Two 16-bit timers:
— Timer T2 ca* operate at high speed (50 *sresolutio*)
— Processor I*depe*de*t PWM mode
— Exter*al Eve*t cou*ter mode
— I*put Capture mode
* Brow*-out Reset (COP8SBE9/SCE9)
* High Curre*t I/Os
— B0 – B3: 10 mA @ 0.3V
— All others: 10 mA @ 1.0V
OTHER FEATURES
* Si*gle supply operatio*:
— 2.7V–5.5V (0°C to +70°C)
— 4.5V–5.5V (−40°C to +125°C)
* Quiet Desig* (low radiated emissio*s)
* Multi-I*put Wake-up with optio*al i*terrupts
* MICROWIRE/PLUS (Serial Peripheral I*terface Compatible)
* Clock Doubler for 20 MHz operatio* from 10 MHz Oscillator, with 0.5 μs I*structio* Cycle
* Eleve* multi-source vectored i*terrupts servici*g:
— Exter*al I*terrupt
— USART (2)
— Idle Timer T0
— Two Timers (each with 2 i*terrupts)
— MICROWIRE/PLUS Serial peripheral i*terface
— Multi-I*put Wake-up
— Software Trap
* Idle Timer with programmable i*terrupt i*terval
* 8-bit Stack Poi*ter SP (stack i* RAM)
* Two 8-bit Register I*direct Data Memory Poi*ters
* True bit ma*ipulatio*
* WATCHDOG a*d Clock Mo*itor logic
* Software selectable I/O optio*s
— TRI-STATE Output/High Impeda*ce I*put
— Push-Pull Output
— Weak Pull Up I*put
* Schmitt trigger i*puts o* I/O ports
* Temperature ra*ge: 0°C to +70°C a*d –40°C to +125°C (COP8SCE9/SDE9)
* Packagi*g: 44 PLCC, 44 LLP a*d 48 TSSOP

COP8SCE9
COP8SDE9
TAG CMOS, EEPROM

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General Description
The FPD95120 is a 320–channel LTPS/CGS driver with Partial Display Memory, a 24–bit RGB video interface and enhanced display quality. It provides 320 output source drivers with a 1:3 glass multiplex ratio. It includes a 230,400–bit memory for partial display modes, a timing controller with glass interface level-shifters, AC and DC VCOM drive schemes and glass power supply circuits. The output format can be configured to drive arbitrary display resolutions up to 320RGB columns. Advanced processing features enable up-scaling of incoming video to accommodate legacy graphics. There is also an upscale function for the Partial Display window to enable larger window sizes.
The on-chip Partial Display Memory is configurable in window size, location and color depth. This memory can support partial display windows such as 240x320 in 3–bit mode and 320x720 in 1–bit color mode. The partial display memory can be used to self-refresh a region of the display in a reduced power state or as an overlay for OSD and alpha-blending features.
The FPD95120 also includes independent RGB gamma curve adjustments as well as user-definable color palettes for 1–bit and 3–bit Partial Display modes.
A low-speed serial interface (LoSSI) is provided to control display operating modes and provide access to the Partial Display Memory. This interface can support both 8–bit and 9– bit protocols. A standard command set is supported to set display modes and operating parameters. Customized register profiles associated with each command are loaded from an on-chip EEPROM. Registers can also be directly accessed by using the Register Access Mode

Features
*Power Savings
*Self-refreshed Partial Display Mode
*Provides timing signal for on-glass charge-sharing circuit
*Standard Command Set
*Registers initialized from on-chip EEPROM
*Command-triggered profiles can change register settings for modes/gamma settings
*Eliminates frequent host SW changes to update register settings
*8 user-defined display configurations
*Programmable Settings
*Display resolution and glass signal timing
*Video interface timing auto-learning circuit
*VID_XFR output reduces tearing in partial mode
*Gamma curves and VCOM adjustment
*Advanced Display Features (evaluation only)
*Configurable Partial Mode Window size, location and color depth
*Self-refreshed partial display mode supports 1–bit and 3– bit depths
*OSD function with Partial RAM data in video mode
*Alpha blending, including transparent mode
*Video 2x upscale with programmable border
*Partial Window 2x upscale with border color
*Interfaces
*Serial Interface (LoSSI) for commands, register access and partial memory access
*24–bit RGB Video interface
*MPL1 high-speed serial interface

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General Description
The LM2506 device adapts RGB style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. The LM2506 supports one RGB display at up to 18-bit color depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz PCLK) is supported. A mode pin configures the device as a Serializer (SER) or Deserializer (DES) so the same chip can be used on both sides of the interface.
The interconnect is reduced from 22 signals to only 3 active signals with the LM2506 chipset easing flex interconnect design, size constraints and cost.
The LM2506 in SER mode resides beside an application, graphics or baseband processor and translates a parallel bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near the display module.
When the Power_Down (PD*) input is asserted on the SER, the MDn and MC line drivers are powered down to save current. The DES can be controlled by a separate Power-Down input or via a signal from the SER (PDOUT*).
The LM2506 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 μA IB current (Class 0).

Features
*RGB Display Interface support up to 800 x 300 1⁄2SVGA formats
*MPL-Level 0 Physical Layer using two data and one clock signal
*Low Power Consumption
*Pinout mirroring enables straight through layout with minimal vias
*Level translatio*betwee*host and display
*Auto Power Dow*o*STOP PCLK
*Link power dow*mode reduces quiescent power under < 10 μA
*1.74V to 2.0V core / analog supply voltage range
*1.74V to 3.0V I/O supply voltage range
*−30C to 85C Operating temperature range System Benefits
*Small Interface
*Low Power
*Low EMI
*Intrinsic Level Translation


LM2506GR
LM2506SQ

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General Description
The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps serializer/ deseralizer (SerDes) for high-speed bidirectional serial data transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. The SCAN25100 integrates precision delay calibration measurement (DCM) circuitry that measures link delay components to better than ± 800 ps accuracy.
The SCAN25100 features independent transmit and receive PLLs, on-chip oscillator, and intelligent clock management circuitry to automatically perform remote radio head synchronization and reduce the cost and complexity of external clock networks. The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable transmitter deemphasis, receiver equalization, speed rate selection, internal
pattern generation/verification, and loop back modes. In addition to at-speed BIST, the SCAN25100 includes IEEE 1149.1 and 1149.6 testability.

Features
■ Exceeds LV and HV CPRI voltage and jitter requirements
■ 2457.6, 1228.8, and 614.4 Mbps operation
■ Integrated delay calibration measurement (DCM) directly measures T14 and Toffset delays to ≤ ± 800 ps

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General Description
LM95214 is an 11-bit digital temperature sensor with a 2-wire System Management Bus (SMBus) interface that can very accurately monitor the temperature of four remote diodes as
well as its own temperature. The four remote diodes can be external devices such as microprocessors, graphics processors that target the ideality of a 2N3904 transistor or diodeconnected 2N3904s.
The LM95214 reports temperature in two different formats for +127.875°C/–128°C range and 0°C/255°C range. The LM95214 TCRIT1, TCRIT2 and TCRIT3 outputs are triggered when any unmasked channel exceeds its corresponding programmable limit and can be used to shutdown the system, to turn on the system fans or as a microcontroller interrupt function.
The current status of the TCRIT1, TCRIT2 and TCRIT3 pins can be read back from the status registers. Mask registers are available for further control of the TCRIT outputs.
Two LM95214 remote temperature channels have programmable digital filters while the other two remote channels utilize a fault-queue to minimize unwanted TCRIT events when temperature spikes are encountered.
For optimum flexibility and accuracy, each LM95214 channel includes registers for offset correction. A three-level address pin allows connection of up to 3 LM95214s to the same SMBus master. The LM95214 includes power saving functions such as: programmable conversion rate, shutdown mode, and disabling of unused channels.

Features
■ Accurately senses die temperature of 4 remote ICs or diode junctions and local temperature
■ Programmable digital filters and analog front end filter
■ 0.125°C LSb temperature resolution
■ 0.03125°C LSb remote temperature resolution with digital filter enabled
■ +127.875°C/–128°C and 0°C/255°C remote ranges
■ Remote diode fault detection, model selection and offset correction
■ Mask and status register support
■ 3 programmable TCRIT outputs with programmable shared hysteresis and Fault-Queue
■ Programmable conversion rate and shutdown mode oneshot conversion control
■ SMBus 2.0 compatible interface, supports TIMEOUT
■ Three-level address pin
■ 14-pin LLP package

Key Specifications
■ Local Temperature Accuracy ±2.0°C (max)
■ Remote Diode Temperature Accuracy ±1.1°C (max)
■ Supply Voltage 3.0V to 3.6V
■ Average Supply Current
(1Hz conversion rate) 0.57 mA (typ)

Applications
■ Processor/Computer System Thermal Management (e.g. Laptop, Desktop, Workstations, Server)
■ Electronic Test Equipment
■ Office Electronics
TAG Diode, Sensor

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General Description
NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change.

 The ADC14C065, ADC14C080, ADC14C095, and ADC14105 are high-performance CMOS analog-to-digital converters capable of converting analog input signals into 14-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance.
A  unique sample-and-hold stage yields a full-power bandwidth of 1GHz. The ADC14C065/080/095/105 may be operated from a single +3.3V power supply and consumes low power.

 A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C065/080/095/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2’s complement) and duty cycle
stabilizer are pin-selectable.
 
 The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14C065/080/095/105 is available in a 32-lead LLP package and operates over the industrial temperature range

Features
*1 GHz Full Power Bandwidth
* Internal sample-and-hold circuit
* Low power consumption
* Internal precision reference
* Data Ready output clock
* Clock Duty Cycle Stabilizer
* Single +3.3V supply operation
* Power-down mode
* Offset binary or 2’s complement output data format
* 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)

Key Specifications
* For ADC14C105
* Resolution 14 Bits
* Conversion Rate 105 MSPS SNR (fIN = 240 MHz) 72 dBFS (typ)
* SFDR (fIN = 240 MHz) 83 dBFS (typ)
* Full Power Bandwidth 1 GHz (typ)
* Power Consumption 400 mW (typ)

Applications
* High IF Sampling Receivers
* Wireless Base Station Receivers
* Test and Measurement Equipment
*Communications Instrumentation
*Portable Instrumentation
TAG bit, Converter

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General Description
Note: This product is currently in development. - ALL specifications are design targets and are subject to change.

 The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.

 The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Bit Error Rate, (BER).
 
 The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage
between 0.8V and 1.2V.
The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate. The ADC can be programmed into the 1:2 Output Mode where the data is output on the Dc and Dd channels at the rate of the input clock.

 The converter typically consumes less than 20 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial
(-40°C ≤ TA ≤ +85°C) temperature range.

Features
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ 1:2 or 1:4 Selectable Output Demux
■ Clock Phase Adjust for Multiple ADC Synchronization
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
■ Test pattern

 Key Specifications
■ Resolution 8 Bits
■ Max Conversion Rate 3 GSPS (min)
■ Bit Error Rate (BER) 10-18 (typ)
■ ENOB @ 748 MHz Input 7.0 Bits (typ)
■ SNR @ 748 MHz 44 dB (typ)
■ Full Power Bandwidth 3 GHz (typ)
■ Power Consumption
— Operating 1.8 W (typ)
— Power Down Mode 20 mW (typ)

Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation

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General Description
 The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.

 The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

 Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and
used as a single 3 GSPS ADC. The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

Features
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ Interleave Mode for 2x Sample Rate
■ Multiple ADC Synchronization Capability
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Fine Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock

Key Specifications
■ Resolution 8 Bits
■ Max Conversion Rate 1.5 GSPS (min)
■ Bit Error Rate 10-18 (typ)
■ ENOB @ 748 MHz Input 7.25 Bits (typ)
■ DNL ±0.15 LSB (typ)
■ Power Consumption
■ — Operating 1.8 W (typ)
— Power Down Mode 3.5 mW (typ)

Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation

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