General description
The NE1617A is an accurate two-channel temperature monitor. It measures the temperature of itself and the temperature of a remote sensor. The remote sensor is a diode connected transistor. This can be in the form of either a discrete NPN/PNP, such as the 2N3904/2N3906, or a diode connected PNP built into another die, such as is done on some Intel microprocessors.
The temperature of both the remote and local sensors is stored in a register that can be read via a 2-wire SMBus. The temperatures are updated at a rate that is programmable via the SMBus (the average supply current is dependent upon the update rate—the faster the rate, the higher the current).
In addition to the normal operation, which is to update the temperature at the programmed rate, there is a one-shot mode that will force a temperature update.
There is also an alarm that senses either an overtemperature or undertemperature condition. The trip points for this alarm are also programmable.
The device can have 1 of 9 addresses (determined by 2 address pins), so there can be up to 9 of the NE1617A on the SMBus.
can also be put in standby mode (in order to save power). This can be done either with software (over the SMBus) or with hardware (using the STBY pin).

Features
*Replacement for Maxim MAX1617 and Analog Devices ADM1021
*Monitors local and remote temperature
*Local (on-chip) sensor accuracy:
-±2 °C at 60 °C to 100 °C
-±3 °C at -40 °C to 125 °C
*Remote sensor accuracy:
-±3 °C at 60 °C to 100 °C
-±5 °C at -40 °C to 125 °C
*No calibration required
*Programmable overtemperature/undertemperature alarm
*SMBus 2-wire serial interface up to 100 kHz
*3 V to 5.5 V supply range; 5.5 V tolerant
*70 mA supply current in operating mode
*3 mA (typical) supply current in standby mode
*ESD protection exceeds 2000 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
*Latch-up testing is done to JEDEC standard JESD78, which exceeds 100 mA
*Small 16-lead SSOP (QSOP) package

Applications
*Desktop computers
*Notebook computers
*Smart battery packs
*Industrial controllers
*Telecommunications equipment

NE1617ADS

General description
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier with a digital I2S audio input. It is available in a HVQFN48 package with exposed die paddle. The exposed die paddle technology enhances the thermal and electrical performances of the device.
The TFA9812 features digital sound processing and audio power amplification. It supports I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed because the key features are controlled by hardware pin connections.
A continuous time output power of 2 ´ 12 W (RL = 8 W, VDDP = 15 V) is supported without an external heat sink. Due to the implementation of a programmable thermal foldback even for high supply voltages, higher ambient temperatures, and/or lower load impedances, the device operates without sound interrupting behavior.
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence required). It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust.
A modulation technique is applied for the TFA9812, which supports common mode choke approach (1 common mode choke only per BTL amplifier stage). This minimizes the number of external components.

Features
*General features
-3.3 V and 8 V to 20 V external power supply
-High efficiency and low power dissipation
-Speaker outputs fully short circuit proof across load, to supply lines and ground
-Pop noise free at power-up/power-down and sample rate switching
-Low power Sleep mode
-Overvoltage and undervoltage protection on the 8 V to 20 V power supply
-Undervoltage protection on the 3.3 V power supply
-Overcurrent protection (no audible interruptions)
-Overdissipation protection
-Thermally protected and programmable thermal foldback
-Clock error protection
-I2C mode control or Legacy mode (i.e. no I2C) control
-Four different I2C addresses supported
-Internal Phase-Locked Loop (PLL) without using external components
-No high system clock required (PLL is able to lock on BCK)
-No external heat sink required
-5 V tolerant digital inputs
-Supports dual coil inductor application
-Easy application and limited external components required
*DSP features
-Digital parametric 10-band equalizer
-Digital volume control per channel
-Selectable +24 dB gain boost
-Analog interface to digital volume control in Legacy mode
-Digital clip level control
-Soft and hard mute
-Thermal foldback threshold temperature control
-De-emphasis
-Output power limiting control
-Polarity switch
-Four Pulse Width Modulation (PWM) switching frequency settings
*Audio data input interface format support
-Master or slave Master Clock (MCLK), Bit Clock (BCK) and Word Select (WS) signals
-Philips I2S, standard I2S
-Japanese I2S, Most Significant Bit (MSB) justified
-Sony I2S, Least Significant Bit (LSB) justified
-Sample rates from 8 kHz to 192 kHz

Applications
*Digital-in Class-D audio amplifier applications
*CRT and flat-panel television sets
*Flat-panel monitors
*Multimedia systems
*Wireless speakers
*Docking stations for MP3 players

TFA9812HN

General description
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (-40 °C to +85 °C) temperature range.

Features
*High speed operation
*Fully static operation
*5 V, 10 V, and 15 V parametric ratings
*Standardized symmetrical output characteristics
*Operates across the full industrial temperature range -40 °C to +85 °C
*Complies with JEDEC standard JESD 13-B
*ESD protection:
-HBM JESD22-A114E exceeds 2000 V
-MM JESD22-A115-A exceeds 200 V

Applications
*Industrial

HEF4020BP, HEF4020BT

General description
The IP4281CZ10 is designed for HDMI interface protection. The device includes high-level ElectroStatic Discharge (ESD) protection diodes for the TMDS signal lines.
All TMDS intra-pairs are protected by a special diode configuration offering a low line capacitance of only 0.7 pF. These diodes provide protection to downstream components from ESD voltages up to ±8 kV contact according to IEC 61000-4-2, level 4.

Features
*Pb-free, RoHS compliant and free of Halogen and Antimony (dark green compliant)
*ESD protection for HDMI and other LVDS data lines
*All TMDS lines with integrated rail-to-rail clamping diodes for downstream ESD protection of ±8 kV according to IEC61000-4-2, level 4
*Matched 0.5 mm trace spacing
*TMDS lines with £ 0.05 pF matching capacitance between TMDS pairs
*Line capacitance of only 0.7 pF for each channel
*4-channel, 10-terminal Ultra-Thin Leadless Package (UTLP)
*HDMI 1.3a compliant

Applications
The IP4281CZ10 is designed for HDMI receiver and transmitter port protection:
*TV, monitor
*Notebook, main board graphics card and ports
*Set-top box and game consoles
*DVD recorder and player

General description
The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) host controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 are fully compliant with Universal Serial Bus Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1.
Integrated high performance USB transceivers allow the ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds.
The ISP1562 is fully compatible with various Operating System (OS) drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux.
The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2.
The ISP1562 is ideally suited for use in Hi-Speed USB mobile applications and embedded solutions. The ISP1562 uses a 12 MHz crystal.

Features
*Complies with Universal Serial Bus Specification Rev. 2.0
*Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
*Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a
*One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0
*Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard
*Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold
*CLKRUN support for mobile applications, such as internal notebook design
*Configurable subsystem ID and subsystem Vendor ID through external EEPROM
*Digital and analog power separation for better ElectroMagnetic Interference (EMI) and
ElectroStatic Discharge (ESD) protection
*Supports hot Plug and Play and remote wake-up of peripherals
*Supports individual power switching and individual overcurrent protection for downstream ports
*Supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the Original USB host controller and the Hi-Speed USB host controller
*Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions
*Supports dual power supply: PCI Vaux(3V3) and VCC
*Operates at +3.3 V power supply input
*Low power consumption
*Full industrial operating temperature range from -40 °C to +85 °C
*Full-scan design with high fault coverage (93 % to 95 %) ensures high quality
*Available in LQFP100 package

Applications
*Digital consumer appliances
*Notebook
*PCI add-on card
*PC motherboard
*Set-Top Box (STB)
*Web appliances

ISP1562BE

General description
The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
The ISP1505 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) and any system chip set to interface with the physical layer of the USB through a 12-pin interface.
The ISP1505 can interface to the link with digital I/O voltages in the range of 1.65 V to 3.6 V.
The ISP1505 is available in HVQFN24 package.

Features
*Fully complies with:
- Universal Serial Bus Specification Rev. 2.0
- UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
*Interfaces to host and peripheral cores; optimized for stand-alone and embedded host applications with an external VBUS supply; stand-alone peripheral cores, and Session Request Protocol (SRP)-capable peripheral cores
*Complete Hi-Speed USB physical front-end solution that supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
- Integrated 45 W ± 10 % high-speed termination resistors, 1.5 kW ± 5 % full-speed device pull-up resistor, and 15 kW ± 5 % host termination resistors
- Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
- USB clock and data recovery to receive USB data up to ±500 ppm
- Insertion of stuff bits during transmit and discarding of stuff bits during receive
- Non-Return-to-Zero Inverted (NRZI) encoding and decoding
- Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
*Supports SRP for reduced power consumption
- Complete control over bus resistors
- Data line and VBUS pulsing session request methods
- Integrated VBUS voltage comparators
*Highly optimized ULPI compliant
- 60 MHz, 8-bit interface between the core and the transceiver
- Supports 60 MHz output clock configuration
- Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:
19.2 MHz (ISP1505ABS) and 26 MHz (ISP1505CBS)
- Fully programmable ULPI-compliant register set
- Internal Power-On Reset (POR) circuit
*Flexible system integration and very low current consumption, optimized for portable devices
- Power-supply input range is 3.0 V to 3.6 V
- Internal voltage regulator supplies 3.3 V and 1.8 V
- Supports external VBUS charge pump
- External VBUS source is controlled using the PSW_N pin; open-drain PSW_N allows per-port or ganged power control
- FAULT input pin to monitor the external VBUS supply status
- Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage pins minimize crosstalk
- Typical operating current of 10 mA to 48 mA, depending on the USB speed and bus utilization
- Typical suspend current of 35 mA
*Full industrial grade operating temperature range from -40 °C to +85 °C
*4 kV ElectroStatic Discharge (ESD) protection on pins DP, DM, VBUS and GND
*Available in a small HVQFN24 (4 mm ´ 4 mm) Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free package

Applications
*Digital still camera
*Digital TV
*Digital Video Disc (DVD) recorder
*External storage device, for example:
- Magneto-Optical (MO) drive
- Optical drive: CD-ROM, CD-RW, DVD
- Zip drive
*Mobile phone
*MP3 player
*PDA
*Printer
*Scanner
*Set-Top Box (STB)
*Video camera

ISP1505C, ISP1505ABS, ISP1505CBS

DESCRIPTION
The NE/SA612A is a low-power VHF monolithic double-balanced mixer with on-board oscillator and voltage regulator. It is intended for low cost, low power communication systems with signal frequencies to 500MHz and local oscillator frequencies as high as 200MHz. The mixer is a “Gilbert cell” multiplier configuration which provides gain of 14dB or more at 45MHz.
The oscillator can be configured for a crystal, a tuned tank operation, or as a buffer for an external L.O. Noise figure at 45MHz is typically below 6dB and makes the device well suited for high performance cordless phone/cellular radio. The low power consumption makes the NE/SA612A excellent for battery operated equipment. Networking and other communications products can benefit from very low radiated energy levels within systems. The NE/SA612A is available in an 8-lead dual in-line plastic package and an 8-lead SO (surface mounted miniature package).

FEATURES
*Low current consumption
*Low cost
*Operation to 500MHz
*Low radiated energy
*Low external parts count; suitable for crystal/ceramic filter
*Excellent sensitivity, gain, and noise figure

APPLICATIONS
*Cordless telephone
*Portable radio
*VHF transceivers
*RF data links
*Sonabuoys
*Communications receivers
*Broadband LANs
*HF and VHF frequency conversion
*Cellular radio mixer/oscillator

NE612AN, NE612AD, SA612AN, SA612AD

General description
 The 74AHC/AHCT245 is a high-speed Si-gate CMOS device.
The 74AHC/AHCT245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
The 74AHC245/74AHCT245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.

Features
* Balanced propagation delays
* All inputs have a Schmitt-trigger action
* Inputs accepts voltages higher than VCC
* For 74AHC245 only: operates with CMOS input levels
* For 74AHCT245 only: operates with TTL input levels
* ESD protection:
* HBM JESD22-A114E exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V
* CDM JESD22-C101C exceeds 1000 V
* Multiple package options
* Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHCT245D
74AHCT245PW
74AHCT245BQ

General description
The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
+ JESD8-7 (1.2 V to 1.95 V)
+ JESD8-5 (1.8 V to 2.7 V)
+ JESD8-B (2.7 V to 3.6 V)
* ESD protection:
+ HBM JESD22-A114E Class 3A exceeds 5000 V
+ MM JESD22-A115-A exceeds 200 V
+ CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G386GW
74AUP1G386GM
74AUP1G386GF

General description
The NX3L1G66 provides one single pole, single-throw analog switch function. It has two
input/output terminals (Yand Z) and an active HIGH enable input pin (E). When E is LOW,
the analog switch is turned off.
Schmitt trigger action at the enable input (E) makes the circuit tolerant to slower input rise
and fall times across the entire VCC range from 1.4 V to 3.6 V.
The NX3L1G66 allows signals with amplitude up to VCC to be transmitted from Y to Z; or
from Z to Y. Its low ON resistance (0.5 W) and flatness (0.13 W) ensures minimal
attenuation and distortion of transmitted signals.

Features
* Wide supply voltage range from 1.4 V to 3.6 V
* Very low ON resistance (peak):
+ 1.6 W (typical) at VCC = 1.4 V
+ 1.0 W (typical) at VCC = 1.65 V
+ 0.55 W (typical) at VCC = 2.3 V
+ 0.50 W (typical) at VCC = 2.7 V
*  High noise immunity
*  ESD protection:
+ HBM JESD22-A114E Class 3A exceeds 7500 V
+ MM JESD22-A115-A exceeds 200 V
+ CDM AEC-Q100-011 revision B exceeds 1000 V
*  CMOS low-power consumption
*  Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
*  Direct interface with TTL levels at 3.0 V
*  Control input accepts voltages above supply voltage
* High current handling capability (350 mA continuous current under 3.3 V supply)
* Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Applications
* Cell phone
* PDA
* Portable media player

NX3L1G66GM