GENERAL DESCRIPTION
The Micron® QDR™II (Quad Data Rate™) synchronous, pipelined burst SRAM employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process.
The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.
GENERAL DESCRIPTION (continued) Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation.
All synchronous inputs pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#).
Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation.
The SRAM operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus.

FEATURES
*DLL circuitry for accurate output data placement
*Separate independent read and write data ports with concurrent transactions
*100 percent bus utilization DDR READ and WRITE operation
*Fast clock to valid data times
*Full data coherency, providing most current data
*Two-tick burst counter for low DDR transaction size
*Double data rate operation on read and write ports
*Two input clocks (K and K#) for precise DDR timing at clock rising edges only
*Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device
*Single address bus
*Simple control logic for easy depth expansion
*Internally self-timed, registered writes
*+1.8V core and HSTL I/O
*Clock-stop capability
*15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
*User-programmable impedance output
*JTAG boundary scan

MT54W4MH9B, MT54W2MH18B, MT54W1MH36B

GENERAL DESCRIPTION
The Micron® MT8LD864A X, MT16LD1664A X and MT32LD3264A X are randomly accessed 64MB, 128MB and 256MB memories organized in a x64 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (A0-A11) at RAS# time and 11/12 bits (A0-A11) at CAS# time.
READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location.

FEATURES
*Eight-CAS# ECC pinout in a 168-pin, dual in-line memory module (DIMM)
*64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64)
*Nonbuffered
*High-performance CMOS silicon-gate process
*Single +3.3V ±0.3V power supply
*All inputs, outputs and clocks are LVTTLcompatible
*4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms
*Extended Data-Out (EDO) PAGE MODE access cycle
*Serial presence-detect (SPD)

MT8LD864A, MT16LD1664A, MT8LD864AG-5X, MT16LD1664AG-5X, MT32LD3264AG-5X

General Description
The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quadbank DRAM.
The 1Gb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 1Gb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte.
The 1Gb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible.

Features
*VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
*Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
*Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
*Differential clock inputs (CK and CK#)
*Commands entered on each positive CK edge
*DQS edge-aligned with data for READs; centeraligned with data for WRITEs
*DLL to align DQ and DQS transitions with CK
*Four internal banks for concurrent operation
*Data mask (DM) for masking write data (x16 has two–one per byte)
*Programmable burst lengths: 2, 4, or 8
*Auto Refresh and Self Refresh Modes
*Longer lead TSOP for improved reliability (OCPL)
*2.5V I/O (SSTL_2 compatible)
*Concurrent auto precharge option is supported
*tRAS lockout supported (tRAP = tRCD)

MT46V128M8, MT46V64M16

GENERAL DESCRIPTION
The MT12D436 and MT24D836 are randomly accessed 16MB and 32MB solid-state memories organized in a x36 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits, which are entered 11 bits (A0 -A10) at a time. RAS# is used to latch the first 11 bits and CAS# the latter 11 bits. A READ or WRITE cycle is selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of CAS#. Since WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle.

FEATURES
*JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module (SIMM)
*16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity versions
*High-performance CMOS silicon-gate process
*Single 5V ±10% power supply
*All inputs, outputs and clocks are TTL-compatible
*Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN
*2,048-cycle refresh distributed across 32ms
*FAST PAGE MODE (FPM) access cycle
*Multiple RAS# lines allow x18 or x36 widths

MT24D836, MT12D436G-XX, MT12D436M-XX

GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion CE2#, CE2), burst control inputs (ADSC#, ADSP#,ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version.
Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#).
Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd# controls DQd’s and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions.
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. Users can choose either a 3.3V or 2.5V I/O version. The device is ideally suited for 486, Pentium®, 680x0 and PowerPC systems and those systems that benefit from a wide synchronous data bus.
The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications.

FEATURES
*Fast clock and OE# access times
*Single +3.3V +0.3V/-0.165V power supply (VDD)
*Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
*SNOOZE MODE for reduced-power standby
*Common data inputs and data outputs
*Individual BYTE WRITE control and GLOBAL WRITE
*Three chip enables for simple depth expansion and address pipelining
*Clock-controlled and registered addresses, data I/Os and control signals
*Internally self-timed WRITE cycle
*Burst control (interleaved or linear burst)
*Automatic power-down for portable applications
*100-pin TQFP package
*165-pin FBGA
*Low capacitive bus loading
*x18, x32, and x36 versions available

MT58L512L18F, MT58L256L32F, MT58L256L36F, MT58L512V18F, MT58L256V32F

General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Features
*PC100- and PC133-compliant
*Fully synchronous; all signals registered on positive edge of system clock
*Internal pipelined operation; column address can be changed every clock cycle
*Internal banks for hiding row access/precharge
*Programmable burst lengths: 1, 2, 4, 8, or full page
*Auto precharge, includes concurrent auto precharge, and auto refresh modes
*Self refresh mode
*64ms, 8,192-cycle refresh
*LVTTL-compatible inputs and outputs
*Single +3.3V ±0.3V power supply

MT48LC32M8A2, MT48LC16M16A2

General Description
The Micron® reduced latency DRAM (RLDRAM®) II is a high-speed memory device designed for high bandwidth data storage—telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges
of the input data clock(s).
Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The μBGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.

Features
*400 MHz DDR operation (800 Mb/s/pin data rate)
*28.8 Gb/s peak bandwidth (x36 at 400 MHz clock frequency)
*Organization
– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36
*8 internal banks for concurrent operation and maximum bandwidth
*Reduced cycle time (20ns at 400 MHz)
*Nonmultiplexed addresses (address multiplexing option available)
*SRAM-type interface
*Programmable READ latency (RL), row cycle time, and burst sequence length
*Balanced READ and WRITE latencies in order to optimize data bus utilization
*Data mask for WRITE commands
*Differential input clocks (CK, CK#)
*Differential input data clocks (DKx, DKx#)
*On-die DLL generates CK edge-aligned data and output data clock signals
*Data valid signal (QVLD)
*32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms)
*144-ball μBGA package
*HSTL I/O (1.5V or 1.8V nominal)
*25–60Ω matched impedance outputs
*2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
*On-die termination (ODT) RTT

MT49H16M18, MT49H8M36

General Description
The Micron® Imaging MT9E001 is a 1/2.5-inch format CMOS active-pixel digital image
sensor with a pixel array of 3,264H x 2,448V.
It incorporates sophisticated on-chip camera functions such as windowing, mirroring, binning and skip modes, and snapshot mode.
It is programmable through a simple two-wire serial interface and has very low power consumption.
The MT9E001 digital image sensor features DigitalClarity® technology—Micron's breakthrough
low-noise CMOS imaging technology that achieves near CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, power consumption, and integration advantages of CMOS.

Features
* DigitalClarity® CMOS imaging technology
* Superior low-light performance
* Low dark current
* Simple two-wire serial interface
* Auto black level calibration
* Support for external mechanical shutter
* Support for external LED or Xenon flash
* High frame rate preview mode with arbitrary downsize scaling from maximum resolution
* Programmable controls: gain, frame size/rate, exposure, left-right and top-bottom image reversal, window size, and panning
* Data interface: parallel
* On-chip phase-locked loop (PLL)
* Bayer pattern down-size scaler
* Four channel shading correction (SC)

Applications
* Digital still cameras
* Cellular phones

MT9E001I12STC

Features
* 200-pin, small-outline, dual in-line memory module (SODIMM)
* Fast data transfer rates: PC1600, PC2100, and PC2700
* Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR SDRAM components
* 512MB (64 Meg x 64), 1GB (128 Meg x 64)
* VDD = VDDQ = +2.5V
* VDDSPD = +2.3V to +3.6V
* 2.5V I/O (SSTL_2 compatible)
* Commands entered on each positive CK edge
* DQS edge-aligned with data for READs; centeraligned with data for WRITEs
* Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
* Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture
* Differential clock inputs CK and CK#
* Four internal device banks for concurrent operation
* Programmable burst lengths: 2, 4, or 8
* Auto precharge option
* Auto Refresh and Self Refresh Modes
* 7.8125μs maximum average periodic refresh interval
* Serial Presence Detect (SPD) with EEPROM
* Programmable READ CAS latency
* Gold edge contacts

MT16VDDF6464H
MT16VDDF12864H

GENERAL DESCRIPTION
 The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits.
It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits.
Each of the x16’s 16,777,216- bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row).
The ad- dress bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option.
An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access.
Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems.
An auto refresh mode is provided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.

FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply

MT48LC16M4A2TG
MT48LC8M8A2TG
MT48LC4M16A2TG