DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
FEATURES
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-4 ns Maximum Propagation Delay
-Fmax = 250 MHz
-3 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 22V10 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C)
*ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*TEN OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION 22LV10D
GAL22LV10D-4LJ, GAL22LV10D-5LJ, GAL22LV10C-7LJ, GAL22LV10C-10LJ
Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
-TTL-Compatible Balanced 8mA Output Drive
*3.3V LOW VOLTAGE 20V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
*ACTIVE PULL-UPS ON ALL PINS
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20LV8D-3LJ, GAL20LV8D-5LJ, GAL20LV8D-7LJ
Description
The Lattice Semiconductor ispGDS™ family is an ideal solution for reconfiguring system signal routing or replacing DIP switches used for feature selection. With today’s demands for customer ease of use, there is a need for hardware which is easily reconfigured electronically without dismantling the system. The ispGDS devices address this challenge by replacing conventional switches with a software configurable solution. Since each I/O pin can be set to an independent logic level, the ispGDS devices can replace most DIP switch functions with about half the pin count, and without the need for additional pull-up resistors. In addition to DIP switch replacement, the ispGDS devices are useful as signal routing cross-matrix switches. This is the only non-volatile device on the market which can provide this flexibility.
With a maximum tpd of 7.5ns, and a typical active Icc of only 25 mA, these devices provide maximum performance at very low power levels. The ispGDS devices may be programmed in-system, using 5 volt only signals, through a simple 4-wire programming interface. The ispGDS devices are manufactured using Lattice Semiconductor’s advanced non-volatile E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
Each I/O macrocell can be configured as an input, an inverting or non-inverting output, or a fixed TTL high or low output. Any I/O pin can be driven by any other I/O pin in the opposite bank. A single input can drive one or more outputs in the opposite bank, allowing a signal (such as a clock) to be distributed to multiple destinations on the board, under software control. The I/Os accept and drive TTL voltage levels.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor is able to deliver 100% field programmability and functionality of all Lattice Semiconductor products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified.
Features
*HIGH-SPEED SWITCH MATRIX
-7.5 ns Maximum Propagation Delay
-Typical Icc = 25 mA
-UltraMOS® Advanced CMOS Technology
*FLEXIBLE I/O MACROCELL
-Any I/O Pin Can be Input, Output, or Fixed TTL High or Low
-Programmable Output Polarity
-Multiple Outputs Can be Driven by One Input
*IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY)
-Programming Time of Less Than One Second
-4-Wire Programming Interface
-Minimum 10,000 Program/Erase Cycles
*E2 CELL TECHNOLOGY
-Non-Volatile Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*APPLICATIONS INCLUDE:
-Software-Driven Hardware Configuration
-Multiple DIP Switch Replacement
-Software Configuration of Add-In Boards
-Configurable Addressing of I/O Boards
-Multiple Clock Source Selection
-Cross-Matrix Switch
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
ISPGDS22-7P, ISPGDS22-7J, ISPGDS18-7P, ISPGDS14-7P, ISPGDS14-7J
Description
The GAL20V8Z and GAL20V8ZD, at 100 μA standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's advanced zero power E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the device in standby mode and is capable of emulating the full functionality of the standard GAL20V8. The GAL20V8ZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Features
*ZERO POWER E2CMOS TECHNOLOGY
-100μA Standby Current
-Input Transition Detection on GAL20V8Z
-Dedicated Power-down Pin on GAL20V8ZD
-Input and Output Latching During Power Down
*HIGH PERFORMANCE E2CMOS TECHNOLOGY
-12 ns Maximum Propagation Delay
-Fmax = 83.3 MHz
-8 ns Maximum from Clock Input to Data Output
-TTL Compatible 16 mA Output Drive
-UltraMOS® Advanced CMOS Technology
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
-Architecturally Similar to Standard GAL20V8
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Battery Powered Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20V8ZD, GAL20V8Z-12QP, GAL20V8Z-12QJ, GAL20V8ZD-12QP
Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 16V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
*ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
*LEAD-FREE PACKAGE OPTIONS
GAL16LV8D-3LJ, GAL16LV8D-5LJ, GAL16LV8C-7LJ, GAL16LV8C-10LJ
Description
The ispLSI 1048E is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Features
*HIGH DENSITY PROGRAMMABLE LOGIC
-8,000 PLD Gates
-96 I/O Pins, Twelve Dedicated Inputs
-288 Registers
-High-Speed Global Interconnects
-Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
-Small Logic Block Size for Random Logic
-Functionally and Pin-out Compatible to ispLSI 1048C
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-fmax = 125 MHz Maximum Operating Frequency
-tpd = 7.5 ns Propagation Delay
-TTL Compatible Inputs and Outputs
-Electrically Eraseable and Reprogrammable
-Non-Volatile
-100% Tested at Time of Manufacture
*IN-SYSTEM PROGRAMMABLE
-In-System Programmable (ISP™) 5V Only
-Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
-Reprogram Soldered Devices for Faster Prototyping
*OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
-Complete Programmable Device Can Combine Glue Logic and Structured Designs
-Enhanced Pin Locking Capability
-Four Dedicated Clock Input Pins
-Synchronous and Asynchronous Clocks
-Programmable Output Slew Rate Control to Minimize Switching Noise
-Flexible Pin Placement
-Optimized Global Routing Pool Provides Global Interconnectivity
-Lead-Free Package Options
ispLSI1048E125LQI, ispLSI1048E100LQI, ispLSI1048E90LQI, ispLSI1048E70LQI
Description
Lattice’s Power Manager II ispPAC-POWR1014/A is general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS® technology. The
ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare)
monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control functions.
The ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs HVOUT1-HVOUT2) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32μs to 2 seconds. The CPLD is programmed using Logi-Builder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the VMON voltage through the I2C bus of the ispPACPOWR1014A device.
The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (ispPAC-POWR1014A only).
Features
*Monitor and Control Multiple Power Supplies
- Simultaneously monitors up to 10 power supplies
- Provides up to 14 output control signals
- Programmable digital and analog circuitry
*Embedded PLD for Sequence Control
- 24-macrocell CPLD implements both state machines and combinatorial logic functions
*Embedded Programmable Timers
- Four independent timers
- 32μs to 2 second intervals for timing sequences
*Analog Input Monitoring
- 10 independent analog monitor inputs
- Two programmable threshold comparators per analog input
- Hardware window comparison
- 10-bit ADC for I2C monitoring (ispPACPOWR1014A only)
*High-Voltage FET Drivers
- Power supply ramp up/down control
- Programmable current and voltage output
- Independently configurable for FET control or digital output
*2-Wire (I2C/SMBus™ Compatible) Interface
- Comparator status monitor
- ADC readout
- Direct control of inputs and outputs
- Power sequence control
- Only available with ispPAC-POWR1014A
*3.3V Operation, Wide Supply Range 2.8V to 3.96V
- In-system programmable through JTAG
- Industrial temperature range: -40°C to +85°C
- 48-pin TQFP package, lead-free option
ispPAC-POWR1014A-01T48I, ispPAC-POWR1014-01T48I,
ispPAC-POWR1014A-01TN48I, ispPAC-POWR1014-01TN48I
General Description
The XPIO™ 110GXS is a fully integrated 10 Gbps serializer/deserializer device designed for high-speed switches and routers that require very low power budget and a small footprint as well. Centering on 10 Gbps speed, the XPIO 110GXS is a versatile chip that is capable of handling applications in various standards, such as OC-192 (9.95 Gbps) and 10GE (10.31 Gbps).
An on-chip low jitter PLL generates all required clocks based on an external reference clock at 1/16 or 1/64 frequency of the serial data rate, which is 622.08 MHz or 155.52 MHz, respectively, for OC-192 applications. An Integrated Limiting Amplifier allows flexibility in placement and reduced bit-error rates (BER).
Fabricated with state-of-the-art CMOS technology, the XPIO 110GXS performs all necessary functions for serial-to-parallel and parallel-to-serial conversions, and consumes less than one third of the power consumed by the more conventional SiGe Bi-CMOS designs.
Features
*Single chip SERDES solution with integrated transmitter and receiver
*Continuous serial operation range from 9.95 Gbps to 10.31 Gbps
*Parallel LVDS data range from 622 Mbps to 644 Mbps
*Low power consumption (800 mW typical)
*Performs 16:1 serialization and 1:16 deserialization
*Embedded Limiting Amplifier enhances receiver sensitivity
*Low-jitter PLL for clock generation
*On-chip Clock Data Recovery circuit
*On-chip FIFO to decouple transmit clocks
*Bit order swap for 10GE operations
*Programmable 4-phase LVDS clock output for easy system design
*Repeating serial data output
*Line loopback, diagnostic loopback, and simultaneous loopback modes
*Frequency Lock Alarm Output
*Programmable differential output swing on both Serial driver and Parallel LVDS driver
*1.3V core voltage and 2.5V I/O voltage
*Supports 10GE (10-Gigabit Ethernet), OC-192, XFP, XSBI and SFI-4.1 interfaces
*269-pin flip-chip BGA (15 x 15 mm body size, 0.8 mm pitch)
*-40 to 85°C operating temperature
LS110GXS-1CF269C, LS110GXS-2CF269C, LS110GXS-1CF269I
Description
The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including:
*Multi-Port Multiprocessor Interfaces
*Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)
*Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)
*Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces
The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns.
The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP).
All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the
required I/O outputs.
I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clockCLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs.
Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output.
A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns.
OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto- output delays.
CLK and CLKEN share the same set of I/O pins.
CLKEN disables the register clock when CLKEN = 0.
Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined.
In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays.
All input pins include Schmitt trigger buffers for noise immunity.
These connections are programmed into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration is saved even when the power is emoved from the device.
In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing.
That is, any I/O pin configured as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode).
Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive.
On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later.
Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability.
In addition, in-system programming is supported through the Test Access Port via a special set of private commands.
The ispGDXVA I/Os are designed to withstand “live insertion” system environments.
The I/O buffers are disabled during power-up and power-down cycles.
When designing for “live insertion,” absolute maximum rating conditions for the Vcc and I/O pins must still be met.
Features
*IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY
-Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement
-“Any Input to Any Output” Routing -Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation
-Space-Saving PQFP and BGA Packaging
-Dedicated IEEE 1149.1-Compliant Boundary Scan Test
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.3V Core Power Supply
-3.5ns Input-to-Output/3.5ns Clock-to-Output Delay
-250MHz Maximum Clock Frequency
-TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)
-Low-Power: 16.5mA Quiescent Icc
-24mA IOL Drive with Programmable Slew Rate Control Option
-PCI Compatible Drive Capability
-Schmitt Trigger Inputs for Noise Immunity
-Electrically Erasable and Reprogrammable
-Non-Volatile E2CMOS Technology
*ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
-3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP)
-Change Interconnects in Seconds
*FLEXIBLE ARCHITECTURE
-Combinatorial/Latched/Registered Inputs or Outputs
-Individual I/O Tri-state Control with Polarity Control
-Dedicated Clock/Clock Enable Input Pins (two) or Programmable Clocks/Clock Enables from I/O Pins (20)
-Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
-Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX
-Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins
-Outputs Tri-state During Power-up (“Live Insertion” Friendly)
*DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE
-MS Windows or NT / PC-Based or Sun O/S
-Easy Text-Based Design Entry
-Automatic Signal Routing
-Program up to 100 ISP Devices Concurrently
-Simulator Netlist Generation for Easy Board-Level Simulation
ISPGDX80VA-5T100
ISPGDX80VA-3T100
Description
The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between all of these elements.
The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port.
The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems.
A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options.
The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB).
The GLBs are labeled A0, A1...B7 (Figure 1).
There are a total of 16 GLBs in the ispLSI 1016EA device.
Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and a dedicated input.
All of the GLB outputs are brought back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Features
* HIGH-DENSITY PROGRAMMABLE LOGIC
- 2000 PLD Gates
- 32 I/O Pins, One Dedicated Input
- 96 Registers
- High-Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Functionally Compatible with ispLSI 1016E
* NEW FEATURES
- 100% IEEE 1149.1 Boundary Scan Testable
- ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
- User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin)
- Open-Drain Output Option
* HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 200 MHz Maximum Operating Frequency
- tpd = 4.5 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
- 100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
- Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
- Reprogram Soldered Device for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue Logic and Structured Designs
- Enhanced Pin Locking Capability
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Programmable Output Slew Rate Control to Minimize Switching Noise
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global Interconnectivity
