The IDTAS4624 low on-resistance (RON), low voltage, single-pole/double-throw (SPDT) analog switch operates from a single +1.8 V to +5.5 V supply. The IDTAS4624 features a 0.5Ω (max) RON for its NC switch and a 0.8Ω (max) RON for its NO switch at a +2.7 V supply. It also features break-before-make switching action (2 ns) with tON = 50 ns and tOFF = 40 ns at +3 V. The digital logic input is 1.8 V logic-compatible with a +2.7 V to +3.3 V supply.

*+1.8 V to +5.5 V single-supply operation
*Rail-to-rail signal handling
*1.8 V logic compatibility
*RON match between channels: 0.06Ω (max)
*RON flatness over signal range: 0.15Ω (max)
*NC Switch RON: 0.5Ω max (+2.7 V Supply)
*NO Switch RON: 0.8Ω max (+2.7 V Supply)
*Low crosstalk: -68dB (100 kHz)
*High Off-isolation: -64dB (100 kHz)
*THD: 0.03%
*50 nA (max) supply current
*Low leakage currents: 1 nA (max) at TA = +25°C
*6-pin SOT-23 package

*Speaker headset switching
*MP3 players
*Battery-operated equipment
*Audio and video signal routing
*PCMCIA cards
*Cellular phones


댓글을 달아 주세요 Comment

The IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

*Guaranteed Low Skew < 25ps (max)
*Very low duty cycle distortion < 125ps (max)
*High speed propagation delay < 1.75ns (max)
*Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
*Up to 1GHz operation
*Selectable inputs
*Hot insertable and over-voltage tolerant inputs
*3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
*Selectable differential inputs to six LVDS outputs
*Power-down mode
*2.5V VDD
*Available in VFQFPN package

*Clock distribution

TAG Buffer, Clock, LVDS

댓글을 달아 주세요 Comment

The ICS557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins.

*Packaged in 20-pin TSSOP
*Available in RoHS 5 (green) or RoHS 6 (green and lead free) complaint package
*Supports PCI-Express applications
*Four differential spread spectrum clock outputs
*Spread spectrum for EMI reduction
*Uses external 25 MHz clock or crystal input
*Power down pin turns off chip
*OE control tri-states outputs
*Spread and frequency selection via external pins
*Spread Bypass option available
*Industrial temperature range available

ICS557G-05A, ICS557G-05AT, ICS557G-05ALF, ICS557G-05ALFT

댓글을 달아 주세요 Comment

The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as insystem programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

*Three internal PLLs
*Internal non-volatile EEPROM
*JTAG and FAST mode I2C serial interfaces
*Input Frequency Ranges: 1MHz to 400MHz
*Output Frequency Ranges:
-LVTTL: up to 200MHz
-LVPECL/ LVDS: up to 500MHz
*Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance
-Crystal Frequency Range: 8MHz to 50MHz
*Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
*10-bit post-divider blocks
*Fractional Dividers
*Two of the PLLs support Spread Spectrum Generation capability
*I/O Standards:
-Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
-Inputs - 3.3V LVTTL/ LVCMOS
*Programmable Slew Rate Control
*Programmable Loop Bandwidth Settings
*Programmable output inversion to reduce bimodal jitter
*Redundant clock inputs with glitchless auto and manual switchover options
*JTAG Boundary Scan
*Individual output enable/disable
*Power-down mode
*3.3V VDD
*Available in TQFP and VFQFPN packages


댓글을 달아 주세요 Comment

The QS3L383 provides ten high-speed CMOS TTL-compatible bus switches. The low ON resistance of the QS3L383 allows inputs to be connected to outputs without adding propagation delay and without generating additional ground bounce noise. The Bus Enable (BE) signal turns the switches on. The Bus Exchange (BX) signal provides nibble swap of the AB and CD pairs of signals. This exchange configuration allows byte swapping of buses in systems. It can also be used as a 5-wide 2-to-1 multiplexer and to create low delay barrel shifters, etc.
The QS3L383 is characterized for operation at -40°C to +85°C.

*Enhanced N channel FET with no inherent diode to Vcc
*5Ω bidirectional switches connect inputs to outputs
*Zero propagation delay, zero added ground bounce
*Ultra low power with 0.2μA typical Icc
*Undershoot clamp diodes on all switch and control inputs
*Bus exchange allows nibble swap
*Available in QSOP and SOIC packages

*Hot-swapping, hot-docking
*Voltage translation (5V to 3.3V)
*Resource sharing
*Crossbar switching


댓글을 달아 주세요 Comment

This registered bus exchanger is built using advanced dual metal CMOS technology. The ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA input allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction
changes with CLK.
The ALVCH16270 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The ALVCH16270 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

*0.5 MICRON CMOS Technology
*Typical tSK(o) (Output Skew) < 250ps
*ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
*VCC = 3.3V ± 0.3V, Normal Range
*VCC = 2.7V to 3.6V, Extended Range
*VCC = 2.5V ± 0.2V
*CMOS power levels (0.4μ W typ. static)
*Rail-to-Rail output swing for increased noise margin
*Available in SSOP, TSSOP, and TVSOP packages

*High Output Drivers: ±24mA
*Suitable for heavy loads

*3.3V high speed systems
*3.3V and lower voltage computing systems


댓글을 달아 주세요 Comment

The ICS841S01 is a PLL-based clock generator specifically designed for PCI_Express™Clock
Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.
The ICS841S01 is available in both standard and lead-free 16-Lead TSSOP packages.

*One 0.7V current mode differential HCSL output pair
*Crystal oscillator interface, 25MHz
*Output frequency: 100MHz
*RMS period jitter: 3ps (maximum)
*Cycle-to-cyle jitter: 35ps (maximum)
*I2C support with readback capabilities up to 400kHz
*Spread Spectrum for electromagnetic interference (EMI) reduction
*3.3V operating supply mode
*0°C to 70°C ambient operating temperature
*Available in both standard (RoHS 5) and lead-free (RoHS 6) packages


댓글을 달아 주세요 Comment

The QS5805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of five non-inverting outputs. The QS5805 device provides low propagation delay buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS5805 is characterized for operation at -40°C to +85°C.

*10 CMOS outputs
*Monitor output
*Rail-to-rail output voltage swing
*Input hysteresis for better noise margin
*Guaranteed low skew:
- 0.7ns output skew (same bank)
- 0.8ns output skew (different banks)
- 1.2ns part-to-part skew
*Std., A, and B speed grades
*Available in QSOP and SOIC packages

QS5805A, QS5805B
TAG Clock, CMOS, Driver

댓글을 달아 주세요 Comment

The IDT29FCT520A/B/C contains four 8-bit positive edgetriggered registers.
These may be operated as a dual 2-level or as a single 4-level pipeline.
A single 8-bit input is provided and any of the four registers is available at the 8-bit, 3-state
In the IDT29FCT520A/B/C when data is entered into the first level (I = 2 or I = 1), the existing data in the first level is moved to the second level.
Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0).
This transfer also causes the first level to change.

*Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage supply extremes
*Four 8-bit high-speed registers
*Dual two-level or single four-level push-only stack operation
*All registers available at multiplexed output
*Hold, transfer and load instructions
*Provides temporary address or data storage
*IOL = 48mA (commercial), 32mA (military)
*CMOS power levels (1mW typ. static)
*Substantially lower input current levels than AMD’s bipolar (5mA typ.)
*TTL input and output level compatible
*CMOS output level compatible
*Manufactured using advanced CMOS processing
*Available in 300 mil plastic and hermetic DIP, as well as LCC, SOIC and CERPACK
*Product available in Radiation Tolerant and Radiation Enhanced versions
*Military product compliant to MIL-STD-883, Class B


댓글을 달아 주세요 Comment

The ICS251 is a low cost, single-output, field programmable clock synthesizer.
The ICS251 can generate an output frequency from 314 kHz to 200 MHz and may employ
Spread Spectrum techniques to reduce system electro-magnetic interference (EMI).
Using ICS’ VersaClock™ software to configure the PLL and output, the ICS251 contains a One-Time Programmable (OTP) ROM to allow field programmability.
Programming features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock.
It can replace multiple crystals and oscillators, saving board space and cost.
The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low.
The ICS251 is also available in factory programmed custom versions for high-volume applications.

* 8-pin SOIC package
* Four addressable registers
* Input crystal frequency of 5 to 27 MHz
* Clock input frequency of 3 to 150 MHz
* Output clock frequencies up to 200 MHz
* Configurable Spread Spectrum Modulation
* Operating voltage of 3.3 V
* Replaces multiple crystals and oscillators
* Controllable output drive levels
* Advanced, low-power CMOS process
* Available in RoHS compliant packagingFeatures
* 8-pin SOIC package
* Four addressable registers
* Input crystal frequency of 5 to 27 MHz
* Clock input frequency of 3 to 150 MHz
* Output clock frequencies up to 200 MHz
* Configurable Spread Spectrum Modulation
* Operating voltage of 3.3 V
* Replaces multiple crystals and oscillators
* Controllable output drive levels
* Advanced, low-power CMOS process
* Available in RoHS compliant packaging


댓글을 달아 주세요 Comment