Description
The LXT362 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface and general T1 long and short haul applications. It operates over 22 AWG twisted-pair cables from 0 to 6 kft and offers Line Build Outs and pulse equalization settings for all T1 Line Interface Unit (LIU) applications.
LXT362 provides both a serial port for microprocessor control (Host mode) as well as standalone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS encoding/decoding and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of diagnostic loopback modes can also be selected.

Product Features
*Fully integrated transceiver for Long or Short-Haul T1 interfaces
-Crystal-less digital jitter attenuation
-Select either transmit or receive path
*No crystal or high speed external clock required
*Meets or exceeds specifications in ANSI T1.102, T1.403 and T1.408; and AT&T Pub 62411
*Supports 100 Ω (T1 twisted-pair) applications
*Selectable receiver sensitivity – fully restores the received signal after transmission through a cable with attenuation of either 0 to 26 dB, or 0 to 36 dB @ 772 kHz
*Five Pulse Equalization Settings for T1 short-haul applications
*Four Line Build-Outs for T1 long-haul applications from 0 dB to -22.5 dB
*Transmit/receive performance monitors with Driver Fail Monitor Open and Loss of Signal outputs
*Selectable unipolar or bipolar data I/O and B8ZS encoding/decoding
*Line attenuation indication output in 2.9 dB steps
*QRSS generator/detector for testing or monitoring
*Local, remote, and analog loopback, plus in-band network loopback code generation and detection
*Multiple register serial interface for microprocessor control
*Available in 28-pin PLCC, 44-pin PQFP, and 44-pin LQFP packages

Applications
*ISDN Primary Rate Interface (ISDN PRI)
*CSU/NTU interface to T1 Service
*Wireless Base Station interface
*T1 LAN/WAN bridge/routers
*T1 Mux; Channel Banks
*Digital Loop Carrier - Subscriber Carrier Systems

249033-001

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Description
The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock recovery with proprietary Optimal Signal Processing (OSP™) architecture improves SNR 3 dB over ideal analog filters. All six network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The LXT9763 supports both half- and full-duplex operation at 10 and 100 Mbps.
A fully independent Media Independent Interface (MII) for each port provides maximum control for switch and multi-port adapter applications.
In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED driver outputs for each port. The LXT9763 requires only a single 3.3V power supply.

Product Features
*Six independent IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters.
*Proprietary Optimal Signal Processing™ (OSP™) architecture improves SNR by 3dB over ideal analog filters.
*Baseline wander correction for improved 100BASE-TX performance.
*100BASE-FX fiber-optic capability on all ports.
*Supports both auto-negotiation and legacy systems without auto-negotiation capability.
*JTAG boundary scan.
*Six MII ports for independent PHY port operation.
*Configurable via MDIO port or external control pins.
*Maskable interrupts.
*Very low power 3.3V operation (380 mW per channel, typical).
*208-pin PQFP (0-70 oC ambient temperature range).

Applications
*100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.

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Description
The Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.
Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is powered from a single 3.3V power supply.

Product Features
*3.3V Operation
*IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters
*Auto-negotiation and parallel detection
*MII interface with extended register capability
*Robust baseline wander correction
*Carrier Sense Multiple Access / Collision Detection (CSMA/CD) or full-duplex operation
*JTAG boundary scan
*MDIO serial port or hardware pin configurable
*Integrated, programmable LED drivers
*48-pin Low-profile Quad Flat Package

Applications
*Combination 10BASE-T/100BASE-TX Network Interface Cards (NICs)
*Wireless access points
*Network printers
*10/100 Personal Computer Memory Card International Association (PCMCIA) cards
*Cable Modems and Set-Top Boxes

DJLXT972MLC.A4, WJLXT972MLC.A4

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Description
The CE6353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds, with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including Unified Nordig and DTG.
A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz IF analog signal. Advanced digital filtering of the upper and lower channel enables a single 8 MHz channel SAW filter to be used for 6, 7 and 8 MHz OFDM signal reception. All sampling and other internal clocks are derived from a single 20.48 MHz crystal or a 4 MHz clock input, the tolerance of which may be relaxed as much as 200 ppm.
The CE6353 has a wide frequency capture range able to automatically compensate for the combined offset introduced by the tuner xtal and broadcaster triple frequency offsets.
An on-chip state machine controls all acquisition and tracking operations of the CE6353 as well as controlling the tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead.
Also included in the design is a 7-bit ADC to detect the RF signal strength and thereby efficiently control the tuner RF AGC.
Users have access to all the relevant signal quality information, including input signal power level, signal-to-noise ratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods are programmable over a wide range.
The device is packaged in a 10 x 10 mm 64-pin LQFP and is very low power.

Features
*Compliant with ETSI 300 744 DVB-T, Unified Nordig and DTG performance specifications
*High performance with fast fully blind acquisition and tracking capability
*Low power consumption: less than 0.32 W, and eco-friendly standby and sleep modes
*Digital filtering of adjacent channels
*Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM
*Superior single frequency network performance
*Fast AGC to track out signal fades
*Good Doppler tracking capability
*Enhanced frequency capture range to include triple offsets
*External 4 MHz clock or single low-cost 20.48 MHz crystal, tolerance up to +/-200 ppm
*Automatic mode (2 K/8 K), guard and spectral inversion detection
*Very low driver software overhead due to on-chip state-machine control
*Novel RF level detect facility via a separate ADC

Applications
*Digital terrestrial set-top boxes
*Integrated digital televisions
*Personal video recorders
*PC-TV receivers
*Portable applications

DJCE6353882077, WJCE6353882206, DJCE6353SL9EN882128, WJCE6353SL9G5882170

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Description
The CE6313 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite television transmissions to the European Broadcast Union ETS 300 421 specification. It receives analogue I and Q signals from the tuner, digitises and digitally demodulates this signal, implements the complete DVB/DSS FEC (Forward Error Correction) and descrambling function. The output is in the form of MPEG2 or DSS transport stream data packets. The CE6313 also provides automatic gain control to the RF front-end device.
The CE6313 has a serial 2-wire bus interface to the control microprocessor. Minimal software is required to control the CE6313 because of the built in automatic search and decode control functions.

Features
*Conforms to EBU specification for DVB-S and DirecTV specification for DSS
*On-chip digital filtering supports 1 - 45 MSps symbol rates
*On-chip 60 or 90 MHz dual-ADC
*High speed scanning mode for blind symbol rate/code rate acquisition
*Automatic spectral inversion resolution
*High level software interface for minimum development time
*Up to ±22.5 MHz LNB frequency tracking
*DiSEqC™ v2.2: receive/transmit for full control of LNB, dish and other components
*Compact 64-pin LQFP package (7 x 7 mm)
*A full DVB-S front-end reference design is available, ref. CE9541

Applications
*DVB 1 - 45 MSps compliant satellite receivers
*DSS 20 MSps compliant satellite receivers
*SMATV (Single Master Antenna TV) transmodulators
*Satellite PC applications

DJCE6313, WJCE6313

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General Description
The LXT9782 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The LXT9762 offers the same features and functionality in a six-port device. This data sheet uses the singular designation “LXT97x2” to refer to both devices.
The LXT97x2 interfaces multiple Serial Media Independent Interface (SMII) compliant controllers to 10BASE-T and/or 100BASE-TX media.
All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection.
The LXT97x2 provides three discrete LED drivers for each port, and eight global serial LED outputs. It supports both half- and full-duplex operation at 10 and 100 Mbps and requires only a single 3.3V power supply.

Product Features
*Multiple independent IEEE 802.3-compliant 10/100 ports with integrated filters
*Proprietary Optimal Signal Processing (OSP™) design improves SNR by 3 dB over ideal analog filters
*Robust baseline wander correction for improved 100BASE-TX performance
*100BASE-FX fiber-optic capability on all ports
*Supports both auto-negotiation and legacy systems without auto-negotiation capability
*JTAG boundary scan
*Multiple Serial MII (SMII) ports for independent PHY port operation
*Configurable via MDIO port or external control pins
*Maskable interrupts
*Very low power consumption (400 mW per port, typical)
*3.3V operation
*208-pin PQFP and 272-lead BGA
*0-70oC ambient temperature range

Application
*100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.

LXT9782

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Description
The CE5037 is a fully integrated direct conversion tuner for digital satellite receiver systems. It provides excellent immunity to composite undesired channels. The device also contains a RF Bypass for connecting to a second receiver module.
The CE5037 is simple to use, requiring no alignment or tuning algorithms and uses a minimum number of external components. The device is programmable via a I2C compatible bus.
The CE5037 is qualified for DVB-S2 8PSK receiver applications A complete reference design (CE9542) is available using CE6313 demodulator.

Features
*Direct conversion tuner for quadrature down conversion from L-band to Zero IF
*Symbol rate 1-45 MS/s
*High sensitivity < -83 dBm at 27.5 MS/s Code rate 7/8
*Independent RF AGC and baseband gain control
*Fifth order baseband filters with bandwidth adjustable from 6 to 43 MHz
*Fully integrated alignment-free low phase noise local oscillator
*Selectable RF Bypass
*Low power consumption 0.5W at 3.3V.
*28 pin 5x5 mm QFN Package

Applications
*DVB-S PayTV satellite receivers
*DSS satellite receivers
*DVB-S2 8PSK satellite receivers

WGCE5037882557, WGCE5037SL9FV882558

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General Description
The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical
layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent
Interface (RMII) for switching and other independent port applications. The LXT9761 offers the
same features and functionality in a six-port device. This data sheet uses the singular designation “LXT97x1” to refer to both devices.
All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for
a 10/100BASE-TX or 100BASE-FX connection.
The LXT97x1 provides three discrete LED driver outputs for each port, as well as eight global
serial LED outputs. The device supports both half- and full-duplex operation at 10 Mbps and 100Mbps, and requires only a single 3.3V power supply.

Product Features
*Six or eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters
*3.3V operation
*Optimized for dual-high stacked R45 applications
*Proprietary Optimal Signal Processing™ architecture improves SNR by 3 dB over ideal analog filters
*Robust baseline wander correction 100BASE-FX fiber-optic capability on all ports
*Supports both auto-negotiation and legacy systems without auto-negotiation capability
*JTAG boundary scan
*Multiple Reduced MII (RMII) ports for independent PHY port operation
*Configurable via MDIO port or external control pins.
*Maskable interrupts
*Low power consumption (390 mW per port, typical)
*208-pin PQFP (LXT9761 and LXT9781)
*272-pin PBGA (LXT9781 only)

Applications
*100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.

LXT9781

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Product Features
*IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface
*IEEE 802.3u Auto-Negotiation support
*Digital Adaptive Equalization control
*Link status interrupt capability
*XOR tree mode support
*3-port LED support (speed, link and activity)
*10BASE-T auto-polarity correction
*LAN Connect Interface
*Diagnostic loopback mode
*1:1 transmit transformer ratio support
*Low power (less than 300 mW in active transmit mode)
*Reduced power in “unplugged mode” (less than 50 mW)
*Automatic detection of “unplugged mode”
*3.3 V device
*48-pin Shrink Small Outline Package

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Product Overview
 The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus.
Individually-erasable memory blocks are optimally sized for code and data storage.
Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map.
The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations at 3 V or 12 V VPP.
With the 3 V I/O option, VCC and VPP can be tied together for a simple, ultra-low-power design.
In addition to I/O voltage flexibility, the dedicated VPP input provides complete data protection when VPP ≤ VPPLK.
The device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable OTP data registers.
Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data.
Additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status.
A command User Interface(CUI) serves as the interface between the system processor and internal operation of the device.
A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode.
The device automatically enters APS mode following read cycle completion.
Standby mode begins when the system deselects the flash memory by deasserting CE#.
The deep power-down mode begins when RP# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings.
Combined, these three power-savings features significantly enhanced power consumption
flexibility.

Product Features
* Flexible SmartVoltage Technology
- 2.7 V – 3.6 V Read/Program/Erase
- 12 V for Fast Production Programming
* 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
- Reduces Overall System Power
* High Performance
- 2.7 V– 3.6 V: 70 ns Max Access Time
* Optimized Architecture for Code Plus Data Storage
- Eight 4 Kword Blocks, Top or Bottom Parameter Boot
- Up to One Hundred-Twenty-Seven 32 Kword Blocks
- Fast Program Suspend Capability
- Fast Erase Suspend Capability
* Flexible Block Locking
- Lock/Unlock Any Block
- Full Protection on Power-Up
- WP# Pin for Hardware Block Protection
* Low Power Consumption
- 9 mA Typical Read
- 7 A Typical Standby with Automatic Power Savings Feature (APS)
* Extended Temperature Operation
- 40 °C to +85 °C
* 128-bit Protection Register
- 64 bit Unique Device Identifier
- 64 bit User Programmable OTP Cells
* Extended Cycling Capability
- Minimum 100,000 Block Erase Cycles
* Software
- Intel® Flash Data Integrator (FDI)
- Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice)
- Intel Basic Command Set
- Common Flash Interface (CFI)
* Standard Surface Mount Packaging
- 48-Ball μBGA*/VFBGA
- 64-Ball Easy BGA Packages
- 48-Lead TSOP Package
* ETOX™VIII (0.13 μm) Flash Technology
-16, 32 Mbit
* ETOX™VII (0.18 μm) Flash Technology
- 16, 32, 64 Mbit
* ETOX™VI (0.25 μm) Flash Technology
- 8, 16 and 32 Mbit

28F800C3
28F160C3
28F320C3
28F640C3

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