General Description
The ICS1893BY-10 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893BY-10 supports managed or unmanaged node, repeater, and switch applications.
The ICS1893BY-10 is intended for MII, Node applications that require the Auto-MIDIX feature that automatically corrects crossover errors in plant wiring.
The ICS1893BY-10 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893BY-10 can virtually eliminate errors from killer packets.
The ICS1893BY-10 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity.
The ICS1893BY-10 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automat i c a l l y (using the Auto-Negotiation features). When the ICS1893BY-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.

Features
*Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz
*Fully integrated, DSP-based PMD includes:
-Adaptive equalization and baseline wander correction
-Transmit wave shaping and stream cipher scrambler
-MLT-3 encoder and NRZ/NRZI encoder
*Low-power, 0.35-micron CMOS (typically 400 mW)
*Power-down mode typically 21mW
*Single 3.3-V power supply.
*Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard
*10Base-T and 100Base-TX IEEE 802.3 compliant
*Highly configurable design supports:
-Node, repeater, and switch applications
-Managed and unmanaged applications
-10M or 100M half- and full-duplex modes
-Parallel detection
-Auto-negotiation, with Next Page capabilities
-Auto-MDI/MDIX crossover correction
*MAC/Repeater Interface can be configured as:
-10M or 100M Media Independent Interface
-100M Symbol Interface (bypasses the PCS)
-10M 7-wire Serial Interface
*Clock and crystal supported
*Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
*Available in Industrial Temperature and Lead-Free

ICS1893BYI-10, ICS1893BY-10LF, ICS1893BYI-10LF

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DESCRIPTION
The M830 Series CDR module is specifically designed to regenerate the spectral clock component from an incoming NRZ data stream, incorporating forward error correction, and output a low-jitter clock and retimed complementary data.
The module utilizes a phase-locked loop architecture incorporating a high-stability, low noise SAW VCO to provide extremely low jitter clock and data outputs. The incoming data is frequency doubled to recover the clock component. The clock signal is then filtered by a microwave band pass filter to remove wide band noise and spurious signal. This signal is further filtered using the narrow band SAW VCO based PLL to minimize the noise close to the carrier. The low jitter clock is then used to retime the data and serves as the module’s clock output. The module provides usercontrolled clock phase shifter and output data crossover adjustments to optimize system performance.
PLL lock-in range and loop transfer characteristics are optimized for minimal jitter in accordance with ITU and Bellcore standards for SONET/SDH systems.

FEATURES
*Superior PLL-based jitter performance
*8psec p-p jitter
*0.9Vp-p complementary data outputs
*1 Ul externally adjustable clock phase
*200mVp-p input sensitivity
*Optional adjustable bias @ data input to decision circuit
*Externally adjustable decision threshold

APPLICATIONS
*SONET OC-192 and SDH STM Physical
*Layer and Clock and Data Recovery
*Applications Incorporating Forward
*Error Correction

M830D

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DESCRIPTION
The M2004-02 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package.
The internal high “Q” SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO.
A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz.
The input to the Frequency Synthesizer is provided by selecting between a differential input clock or a single ended input clock.
The output frequency is an integer multiple of the input reference frequency. The multiplying factor is programmed via a 6 bit parallel address.
An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock.
The bandwidth control, low phase noise, and HOLD features make the M2004-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications.

FEATURES
*Output Clock Frequency up to 700MHz
*Internal Low-jitter SAW-based Oscillator
*Intrinsic Jitter <1ps rms (12kHz - 20MHz)
*Differential Input Compatible with LVPECL, LVDS, HSTL, SSTL, etc.
*Dual Input MUX
*Parallel Programming
*Tunable Loop Filter Response
*Differential LVPECL Outputs
*3.3V Operation
*Small 9mm x 9mm SMT Package

APPLICATIONS
*SONET / SDH / 10GbE System Synchronization
*Add / Drop Muxes, Access and Edge Switches
*Line Card System Clock Cleaner / Translator
*Optical Module Clock Cleaner / Translator

M2004-02-500.0000, M2004-02-622.0800, M2004-02-625.0000

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General Description
The ICS1892, an enhanced version of the ICS 1890, is a fully integrated, physical-layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC 8802-3.
The ICS1892 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cable with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1892 can virtually eliminate errors from killer packets.
The ICS1892 supports a broad range of applications: data terminal equipment (network interface cards and motherboards), switches, repeaters, bridges, and routers. Its Media Independent Interface (MII) supports direct chip-to-chip and motherboard-to-daughterboard connections as well as connections to an MII connector and cable. The ICS1892 also provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity.
The ICS1892 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be done manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1892 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote l ink partner and automatically selects the highest-performance operating mode they have in common.

Features
*Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5° to +85° C
*DSP-based baseline wander correction to virtually eliminate killer packets across temperature range of from -5° to +85° C
*Low-power, 0.5-micron CMOS
*Single 5.0-V power supply.
*Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard
*10Base-T and 100Base-TX IEEE 802.3 compliant
*Fully integrated, DSP-based PMD includes:
–Adaptive equalization and baseline wander correction
–Transmit wave shaping and stream cipher scrambler
–MLT-3 encoder and NRZ/NRZI encoder
*Highly configurable design supports:
–Node, repeater, and switch applications
–Managed and unmanaged applications
–10M or 100M half- and full-duplex modes
–Parallel detection
–Auto-negotiation, with Next Page capabilities
*MAC/Repeater Interface can be configured as:
–10M or 100M Media Independent Interface
–100M Symbol Interface (bypasses the PCS)
–10M 7-wire Serial Interface
*Provides Loopback Modes for Diagnostic Functions
*Small Footprint 64-pin Low-Profile LQFP and MQFP packages available

ICS1892Y, ICS1892Y-10, ICS1892Y-14

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GENERAL DESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet.
The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.

FEATURES
*Dual 2:1/1:2 MUX
*Three LVDS outputs
*Three differential inputs
*Differential inputs can accept the following differential levels: LVPECL, LVDS, CML
*Loopback test mode available
*Maximum output frequency: 2.5GHz
*Part-to-part skew: 250ps (maximum)
*Additive phase jitter, RMS: 0.05ps (typical)
*Propagation delay: 550ps (maximum)
*2.5V operating supply
*-40°C to 85°C ambient operating temperature
*Available in both standard and lead-free RoHS compliant packages

ICS85454AK-01, ICS85454AK-01T, ICS85454AK-01LF, ICS85454AK-01LFT

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GENERAL DESCRIPTION
The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability.

FEATURES
*8 Differential LVDS outputs
*CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Maximum output frequency: 700MHz
*Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
*Translates any single-ended input signal to LVDS with resistor bias on nCLK input
*Multiple output enable inputs for disabling unused outputs in reduced fanout applications
*Output skew: 50ps (maximum)
*Part-to-part skew: 550ps (maximum)
*Propagation delay: 2.4ns (maximum)
*3.3V operating supply
*0°C to 70°C ambient operating temperature
*Lead-Free package RoHS compliant

ICS85408BG, ICS85408BGT
ICS85408BGLF, ICS85408BGLFT

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GENERAL DESCRIPTION
The ICS858012 is a high speed 1-to-2 Differentialto-2.5V, 3.3V LVPECL Fanout Buffer and is a member of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS858012 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, LVHSTL and HCSL to be easily interfaced to the input with minimal use of external components. The ICS858012 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in 8space-constrained applications

FEATURES
*Two differential LVPECL outputs
*One differential LVPECL clock input
*IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Output frequency: 2GHz (typical)
*Output skew: <15ps (typical)
*Part-to-part skew: TBD
*Additive phase jitter, RMS: TBD
*Propagation delay: 350ps (typical)
*Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V
*-40°C to 85°C ambient operating temperature
*Availabe in both standard and lead-free RoHS compliant packages

ICS858012AK, ICS858012AKT, ICS858012AKLF, ICS858012AKLFT

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General Description
The AV9155C-44 is a low cost frequency generator designed specifically for desktop and  notebook PC applications with either 3.3V or 5.0V power supply voltage.
Its CPU clocks provide all necessary CPU frequencies for 286, 386 and 486 systems, including support for the latest speeds of processors.
The device uses a 14.318 MHz crystal to generate the CPU and all peripheral clocks for integrated desktop motherboards.
The dual 14.318 MHz clock outputs allows one output for the system and one to be the input to an ICS graphics frequency generator such as the AV9194.
The CPU clock offers the unique feature of smooth, glitchfree transitions from one frequency to the next, making this ideal device to use whenever slowing the CPU speed.
The AV9155C-44 makes a gradual transition between frequencies, so that it obeys the Intel cycle-to-cycle timing specification for 486 systems.
The simultaneous 2X and 1X CPU clocks offer controlled skew to within 1.5ns (max) of each other.

Features
*Compatible with 286, 386, and 486 CPUs
*Supports turbo modes
*Generates communications clock, keyboard clock, floppy disk clock, system reference clock, bus clock and CPU clock
*Output enable tristates outputs
*Up to 100 MHz at 5V or 3.3V
*20-pin DIP or SOIC
*All loop filter components internal
*Skew-controlled 2X and 1X CPU clocks
*Power-down option

AV9155C-44CW20
TAG Generator

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GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed specifically for redundant clock tree designs.
The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer performance.
The ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H).
If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated.

FEATURES
* 5 differential 3.3V LVPECL outputs
* Selectable differential clock inputs
* CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
* VCO range: 200MHz to 500MHz
* External feedback for “zero delay” clock regeneration with configurable frequencies
* Cycle-to-cycle jitter (RMS): 20ps (maximum)
* Output skew: 70ps (maximum), within one bank
* 3.3V supply voltage
* -40°C to 85°C ambient operating temperature
* Pin compatible with MPC993

ICS87993AYI
ICS87993AYIT
TAG Clock, Switch

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General Description
The ICS932S422C is a main clock synthesizer for CK410-generation Intel server platforms.
The ICS932S422C is driven with a 14.318MHz crystal. It generates 5 CPU output pairs up to 400MHz and PCI-Express clocks at 100 or 200 MHz.
The 48 MHz USB clock is an exact 48.000 MHz clock.

Features/Benefits
* Supports spread spectrum modulation, 0 to -0.5% down spread
* Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error
* CPU clocks independent of SRC/PCI clocks
* D2/D3 SMBus address
* Compliant with PCIe Gen II phase noise specifications

Output Features
* 5 - 0.7V current-mode differential CPU pairs
* 4 - 0.7V current-mode differential SRC pair
* 4 - PCI (33MHz)
* 3 - PCICLK_F, (33MHz) free-running
* 1 - 48MHz
* 2 - REF, 14.318MHz

TAG Clock, pcie, Server

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