Description
The IMP811/IMP812 are low-power supervisors designed to monitor voltage levels of 3.0V, 3.3V and 5.0V power supplies in low-power microprocessor (μP), microcontroller (μC) and digital systems. Each features a debounced manual reset input. The IMP811/812 are improved drop-in replacements for the Maxim MAX811/812 with extended temperature specifications to 105°C.
A reset signal is issued if the power supply voltage drops below a preset threshold and is asserted for at least 140ms after the supply has risen above the reset threshold. The IMP811 has an active-low output RESET that is guaranteed to be in the correct state for VCC down to 1.1V. The IMP812 has an active-high output RESET. The reset comparator is designed to ignore fast transients on VCC .
Low power consumption makes the IMP811/IMP812 ideal for use in portable and battery-operated equipment. Available in a compact 4-pin SOT143 package, the devices use minimal board space.

Key Features
*Improved Maxim MAX811/MAX812 replacement
-Specified to 105°C
-New 4.0V threshold option
*6μA supply current
*Monitor 5V, 3.3V and 3V supplies
*Manual reset input
*140ms min. reset pulse width
*Guaranteed over temperature
*Active-LOW reset valid with 1.1V supply (IMP811)
*Small 4-pin SOT-143 package
*No external components
*Power-supply transient-immune design

Applications
*Computers and controllers
*Embedded controllers
*Battery operated systems
*Intelligent instruments
*Wireless communication systems
*PDAs and handheld equipment

IMP812, IMP811LEUS-T, IMP811MEUS-T, IMP812LEUS-T, IMP812MEUS-T

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General Description
This CMOS device is designed for switching PCM-encoded voice or data,under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64kbit/s channels multiplexed to form a 2048kbit/s ST-BUS stream. In addition, the IMP8980D provides microprocessor read and write access to individual ST-BUS (Serial Telecom Bus) channels.

Features
*ST-BUS compatible
*8-line x 32-channel inputs
*8-line x 32-channel outputs
*256 ports non-blocking switch
*Single power supply (+5V)
*30mW power consumption
*Microprocessor-control interface
*Pin-compatible with Mitel MT8980

IMP8980DC, IMP8980DE, IMP8980DP, IMP8980DP/T

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Description
The IMP1233D supply voltage monitor is an improved, low-power replacement for the Dallas Semiconductor DS1233D. Maximum supply current over temperature is a low 20μA, representing over 60 percent lower power as compared to the DS1233D.
The IMP1233D issues an active LOW reset signal whenever the monitored supply is out-of-tolerance. A precision reference and comparator circuit monitor power supply (VCC) level. Tolerance level options are 5-,10- and 15-percent. When an out-of-tolerance condition is detected, an internal power-fail signal is generated which forces an active LOW reset signal. After VCC returns to an in-tolerance condition, the reset signal remains active for 350ms to allow the power supply and system microprocessor to stabilize.
The IMP1233D is designed with a open-drain output stage and operates over the extended industrial temperature range. Devices are available in compact surface mount SOT-223 packages.
Other low power products in this family include the IMP1810/11/12/15/16/17 and IMP1233M.

Key Features
*Improved Dallas DS1233D replacement
-Over 60% lower maximum supply current
*Low Supply Current
-20μA maximum (5.5V)
-15μA maximum (3.6V)
*Automatically restarts a microprocessor after power failure
*350ms reset delay after VCC returns to an in-tolerance condition
*Active LOW power-up reset, 5kΩ internal pull-up
*Precision temperature-compensated voltage reference and comparator
*Eliminates external components
*Motorola 68xxx and HC16 compatible
*Compact surface mount SOT-223 package
*Operating temperature –40°C to +85°C

Applications
*Set-top boxes
*Cellular phones
*PDAs
*Energy management systems
*Embedded control systems
*Printers
*Single board computers

IMP1233DZ-5/T, IMP1233DZ-10/T, IMP1233DZ-15/T

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Description
The IMP809/IMP810 are 3.0V, 3.3V and 5.0V power supply supervisor circuits optimized for low-power microprocessor (μP), microcontroller (μC) and digital systems. The IMP809/810 are improved drop-in replacements for the Maxim MAX809/810 and feature 60% lower supply current.
A reset signal is issued if the power supply voltage drops below a preset reset threshold and is asserted for at least 140ms after the supply has risen above the reset threshold. The IMP809 has an active-low RESET output that is guaranteed to be in the correct state for VCC down to 1.1V. The IMP810 has an active-high RESET output. The reset comparator is designed to ignore fast transients on VCC.
Low supply current makes the IMP809/IMP810 ideal for use in portable and battery operated equipment. The IMP809/IMP810 are available in a compact 3-pin SOT23 package.

Key Features
*Improved Maxim MAX809/MAX810 replacement
-Lower supply current…6μA
-80% lower maximum supply current
*Monitor 5V, 3.3V and 3V supplies
*140ms min. reset pulse width
*Active-low reset valid with 1.1V supply (IMP809)
*Small 3-pin SOT-23 package
*No external components
*Specified over full temperature range
- –40°C to 105°C

Applications
*Embedded controllers
*Battery operated systems
*Intelligent instruments
*Wireless communication systems
*PDAs and handheld equipment

IMP809LEUR-T, IMP809MEUR-T, IMP809JEUR-T, IMP810LEUR-T, IMP810MEUR-T

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Description
The IMP16C554 is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. A programmable baud rate generator is provided to select transmit and receive clock rates from 50Hz to 1.5MHz.
The IMP16C554 is an improved version of the IMP16C550 UART with higher operating speed and lower access time. The IMP16C554 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user’s requirements. The IMP16C554 provides internal loop-back capability for on board diagnostic testing.
The IMP16C554 is fabricated in an advanced 1.2u CMOS process to achieve low drain power and high speed requirements.

Key Features
*16 byte receive FIFO with error flags
*Modem control signal (CTS*, RTS*, DSR*, DTR*, RI* ,CD*)
*Programmable character lengths(5,6,7,8)
*Even, odd, or no parity bit generation and detection
*Status report register
*Independent transmit and receive control
*TLL compatible inputs. outputs
*Software compatible with Ei8250, 1Ei16C550
*460.8kHz transmit/receive operation with 7.372 MHz crystal or external clock source

IMP16C554-CJ68, IMP16C554-LJ68

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General Description
The IMP5115 SCSI terminator is part of IMP's family of high-performance, adaptive, non-linear mode SCSI products, which are designed to deliver true UltraSCSI performance in SCSI applications. The low voltage BiCMOS architecture employed in its design offers performance superior to older linear passive and active techniques. IMP's SCSI termination architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible — typically 35MHz, which is 100 times faster than the older linear regulator/terminator approach used by other manufacturers. Products using this older linear
regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500KHz (see further discussion in the Functional Description section). This new architecture also eliminates the output compensation capacitor required in earlier terminator designs. Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond — providing the highest performance alternative available today.
Another key improvement offered by the IMP5115 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. The IMP5115 architecture is much more tolerant of marginal system integrations.
Recognizing the needs of portable and configurable peripherals, the IMP5115 has a TTL compatible sleep/disable mode. Quiescent current typically 375μA in this mode, while the output capacitance is also less than 3pF. The obvious advantage of extended battery life for
portable systems is inherent in the product's sleep-mode feature. Additionally, the disable function permits factory-floor or productionline configurability, reducing inventory and product-line diversity costs. Field configurability can also be accomplished without physically removing components which, often times results in field returns due to mishandling.
Reduced component count is also inherent in the IMP5115 architecture. Traditional termination techniques require large stabilization and transient protection capacitors of up to 20μF in value and size. The IMP5115 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs.

Key Features
*Ultra-Fast response for Fast-20 SCSI applications
*35MHz channel bandwidth
*3.3V operation
*Less than 3pF output capacitance
*375μA Sleep-mode current
*Thermally self limiting
*No external compensation capacitors
*Implements 8-bit or 16-bit (wide) applications
*Compatible with active negation drivers (60mA/channel)
*Compatible with passive and Active terminations
*Approved for use with SCSI 1, 2, 3 and UltraSCSI
*Hot swap compatible
*Pin-for-pin compatible with DS21S07A/2105

IMP5115CD, IMP5115CDT, IMP5115CDW, IMP5115CDWT, IMP5115CPWP, IMP5115CPWPT

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General Description
The IMP6303 is a 4.0V power supply supervisor circuits optimized for lowpower microprocessor (μP), microcontroller (μC) and digital systems.
A reset signal is issued if the power supply voltage drops below a preset reset threshold and is asserted for at least 140ms after the supply has risen above the reset threshold. The IMP6303 has an active-low RESET output that is guaranteed to be in the correct state for VCC down to 1.1V.
The reset comparator is designed to ignore fast transients on VCC.
Low supply current makes the IMP6303 ideal for use in portable and battery operated equipment. The IMP6303 is available in a compact 3-pin SOT23, TO-92 and 5 pin SOT23-5 packages.

Features
*Monitor 4.0V supply
*140ms min. reset pulse width
*Active-low reset valid with 1.1V supply
*Small 3-pin SOT-23 package
*Small 3-pin TO-92 package
*Small 5-pin SOT-23-5 package
*No external components
*Specified over full temperature range
- –40°C to 105°C

Applications
*Embedded controllers
*Battery operated systems
*Intelligent instruments
*Wireless communication systems
*PDAs and handheld equipment

IMP6303JEUR-T

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General Description
The IMP2119 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10 standards committee for low voltage differential (LVD) termination. Multimode compatibility permits the use of legacy devices on the bus without hardware alterations. Automatic mode selection is achieved through voltage detection on the diffsense line.
The IMP2119 delivers the ultimate in SCSI bus performance while saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The individual high bandwidth drivers also maximize channel separation and reduce channel to channel noise and cross talk. The high bandwidth architecture insures ULTRA3 performance.
When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. In application, this pin is tied to the DIFFSENSE input of the corresponding LVD transceivers. This action enables the LVD transceiver function. DIFFSENSE is capable of supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places the IMP2119 in a high impedance state indicating the presence of an HVD device. Tying the pin LOW places the part in a single-ended mode while also signaling the multimode transceiver to operate in a singleended mode.
Recognizing the needs of portable and configurable peripherals, the IMP2119 have a TTL compatible sleep/disable mode. During this sleep/disable mode, power dissipation is reduced to a meager 15μA while also placing all outputs in a high impedance state. Also during sleep/disable mode, the DIFFSENSE function is disabled and is placed in a high impedance state.
Another key feature of the IMP2119 is the master/slave function. Driving this pin HIGH or floating the pin enables the 1.3V DIFFSENSE reference. Driving the pin LOW disables the on board DIFFSENSE reference and enables use of an external master reference device.

Key Features
*Auto-selectable LVD or single-ended termination
*3.0pF maximum disabled output capacitance
*Fast response, no external capacitors required
*Compatible with active negation drivers
*15μA supply current in disconnect mode
*Logic command disconnects all termination lines
*DIFFSENSE line driver
*Ground driver integrated for single-ended operation
*Current limit and thermal protection
*Hot-swap compatible (single-ended)
*Compatible with SCSI, SPI-2, SPI-3, SPI-4 ULTRA160 and ULTRA320
*Pin compatible with DS2119

IMP2119CPW

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Description
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family of high-performance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach.
The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs.
Reduced component count is inherent with the IMP5111/5112.
The IMP5111/5112 architecture tolerates marginal system designs.
Akey improvement offered by the IMP5111/5112 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance.
Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/5112 can be placed in a sleep mode with a disconnect signal.
Quiescent current is less than 275μA when disabled.
When disabled, the outputs are in a high impedance state with output capacitance less than 3pF.

Key Features
*Ultra-Fast response for Fast-20 SCSI applications
*35MHz channel bandwidth
*3.3V operation
*Less than 3pF output capacitance
*Sleep-mode current less than 275μA
*Thermally self limiting
*No external compensation capacitors
*Implements 8-bit or 16-bit (wide) applications
*Compatible with active negation drivers (60mA/channel)
*Compatible with passive and active terminations
*Approved for use with SCSI 1, 2, 3 and UltraSCSI
*Hot swap compatible
*Pin-for-pin compatible with LX5211 and UC5606 (IMP5111)
*Pin-for-pin compatible with LX5212 and UC5603/5613/5614 (IMP5112)

IMP5112
IMP5111CDP

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DESCRIPTION
 The 9-channel IMP5218 SCSI terminator is part of IMP's family of highperformance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
The IMP5218 has two disconnect pins for SCSI Plug and Play (PnP) applications.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach.
The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. Reduced component count is inherent with the IMP5218.
The IMP5218 architecture tolerates marginal system designs.
A key improvement offered by the IMP5218 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance.
Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5218 can be placed in a sleep mode with two disconnect signals.
When disabled, the quiescent current is typically 375μA, and the outputs are in a high impedance state.

Key Features
* SCSI plug and play
- Dual disconnect pins
- Logic LOW disconnects lines
* Hot swap compatible
* Ultra-Fast response for Fast-20 SCSI applications
* 35MHz channel bandwidth
* 3.5V operation
* Less than 3pF output capacitance
* 375μA disable-mode current
* Thermally self limiting
* No external compensation capacitors
* Implements 8-bit or 16-bit (wide) applications
* Compatible with active negation drivers (60mA/channel)
* Compatible with passive and active terminations
* Approved for use with SCSI 1, 2, 3 and UltraSCSI

IMP5218CDW
IMP5218CDWT
IMP5218CPW
IMP5218CPWT

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