DESCRIPTION
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

FEATURES
*VDD, VDDQ = 2.5V ± 5%
*All inputs and outputs are compatible with SSTL_2 interface
*JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch
*Fully differential clock inputs (CK, /CK) operation
*Double data rate interface
*Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
*Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
*Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
*All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
*Write mask byte controls by DM (DM0 ~ DM3)
*Programmable /CAS Latency 3 and 4 supported
*Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
*Internal 4 bank operations with single pulsed /RAS
*tRAS Lock-Out function supported
*Auto refresh and self refresh supported
*4096 refresh cycles / 32ms
*Half strength and Matched Impedance driver option controlled by EMRS

HY5DU283222Q-4, HY5DU283222Q-45, HY5DU283222Q-5, HY5DU283222Q-55
TAG GDDR, SDRAM

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DESCRIPTION
The HY62U8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62U8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V.

FEATURES
*Fully static operation and Tri-state outputs
*TTL compatible inputs and outputs
*Low power consumption
*Battery backup(LL-part)
-2.0V(min) data retention
*Standard pin configuration
-32pin 525mil SOP
-32pin 400mil TSOP-II (Standard and Reversed)

HY62U8400A, HY62U8400A-E, HY62U8400A-I
TAG CMOS, SRAM

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DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM, LDQM
*Internal four banks operation
*Auto refresh and self refresh
*8192 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or Full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V121620T, HY57V121620LT, HY57V121620T-6, HY57V121620LT-6

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DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)

FEATURES
*Voltage : VDD, VDDQ 3.3V
*All device pins are compatible with LVTTL interface
*90Ball FBGA with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by DQM0,1,2 and 3
*Internal four banks operation
*Auto refresh and self refresh
*4096 Refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks
*Burst Read Single Write operation

HY5V52F-H, HY5V52F-P, HY5V52F-S, HY5V52FP-H, HY5V52FP-P

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DESCRIPTION
The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16 HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM or LDQM
*Internal four banks operation
*Auto refresh and self refresh
*4096 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or Full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V281620HCT-6, HY57V281620HCT-7, HY57V281620HCT-K, HY57V281620HCT-H

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DESCRIPTION
The Hynix HY5V66E(L)F6(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V66E(L)F6(P) is organized as 4banks of 1,048,576 x 16.
HY5V66E(L)F6(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)

FEATURES
*Voltage: VDD, VDDQ 3.3V supply voltage
*All device pins are compatible with LVTTL interface
*60 Ball FBGA (Lead or Lead Free Package)
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM, LDQM
*Internal four banks operation
*Auto refresh and self refresh
*4096 Refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency; 2, 3 Clocks
*Burst Read Single Write operation

HY5V66EF6-5, HY5V66EF6-6, HY5V66EF6-7, HY5V66EF6-H, HY5V66EF6-P

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DESCRIPTION
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V26C (L/S)F is organized as 4banks of 2,097,152x16 HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device balls are compatible with LVTTL interface
*54Ball FBGA (10.5mm x 8.3mm)
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM or LDQM
*Internal four banks operation
*Auto refresh and self refresh
*4096 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY5V26CF-6, HY5V26CF-K, HY5V26CF-H, HY5V26CF-8, HY5V26CF-P, HY5V26CF-S
TAG DRAM

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DESCRIPTION
The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820B is organized as 4banks of 8,388,608x8.
The HY57V56820B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by DQM
*Internal four banks operation
*Auto refresh and self refresh
*8192 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V56820BT-6, HY57V56820BT-K, HY57V56820BT-H, HY57V56820BT-8, HY57V56820BT-P, HY57V56820BT-S, HY57V56820BLT-6, HY57V56820BLT-K, HY57V56820BLT-H, HY57V56820BLT-8, HY57V56820BLT-P, HY57V56820BLT-S

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DESCRIPTION
The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.
HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave).
A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle.
(This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by DQM
*Internal four banks operation
*Auto refresh and self refresh
*4096 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or Full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V64420HGT-K
HY57V64420HGT-H
HY57V64420HGT-P
TAG DRAM

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DESCRIPTION
 The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.

FEATURES
• VDD/VDDQ = 2.5 ~ 2.7V
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• CAS latency 3 supported
• Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• tRAS Lock-out function supported
• Auto refresh and Self refresh supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Full and Half strength driver option controlled by EMRS

HY5DU56422CT-D
HY5DU56822CT-D
HY5DU561622CT-D
TAG DDR SDRAM

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