GENERAL DESCRIPTION
 The HSD16M64D16A is a 16M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy.
Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.
The HSD16M64D16A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
• Part Identification
-HSD16M64D16A-F/10L : 100MHz (CL=3)
-HSD16M64D16A-F/10 : 100MHz (CL=2)
-HSD16M64D16A-F/12 : 125MHz (CL=3)
-HSD16M64D16A-F/13 : 133MHz (CL=3)
-F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 8M x 8bit x 4Banks SDRAM

HSD16M64D16A-13
HSD16M64D16A-12
HSD16M64D16A-10L

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GENERAL DESCRIPTION
 The HMN5128JV Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits. The HMN5128JV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data.
 In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN5128JV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.

FEATURES
* Access time : 70, 85 ns
* High-density design : 4Mbit Design
* Battery internally isolated until power is applied
* Industry-standard 34-pin 512K x 8 pinout
* Unlimited write cycles
* Data retention in the absence of VCC
* 10-years minimum data retention in absence of power
* Automatic write-protection during power-up/power-down cycles
* Data is automatically protected during power loss
* Conventional SRAM operation; unlimited write cycles

FUNCTIONAL DESCRIPTION
 The HMN5128JV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A18) defines which of the 524,288 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable.
 
 When power is valid, the HMN5128JV operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN5128JV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN5128JV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge.

 The HMN5128JV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Powerdown/ power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and all outputs are high impedance. As Vcc falls below approximately 2.5 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 3.0 volts.

HMN5128JV-70
HMN5128JV-85
TAG Module, SRAM

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