GENERAL DESCRIPTION
The HMF1M32M8G is a high-speed flash read only memory (FROM) module containing 1,048,576 words organized in a x32bit configuration. The module consists of eight 512K x 8 FROM mounted on a 72 -pin, single-sided, FR4-printed circuit board. Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V flash or EPROM devices.
Eight chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1, /CE_LL1, /CE_UU2, /CE_UM2, /CE_LM2, /CE_LL2) are used to
enable the module’s 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output..When FROM module is disable condition the module is becoming power standby mode, system designer can get low - power design. All module components may be powered from a single +5V DC power supply and all inputs and outputs are TTL-compatible.

FEATURES
*Access time: 55, 70, 90 and 120ns
*High-density 4MByte design
*High-reliability, low-power design
*Single + 5V ± 0.5V power supply
*Easy memory expansion
*All inputs and outputs are TTL-compatible
*FR4-PCB design
*Low profile 72-pin SIMM
*Minimum 1,000,000 write/erase cycle
*Sector erases architecture
*Sector group protection
*Temporary sector group unprotection

HMF1M32M8G-55, HMF1M32M8G-70, HMF1M32M8G-90, HMF1M32M8G-120

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GENERAL DESCRIPTION
The HMF2M32M8A is a high-speed flash read only memory (FROM) module containing 2,097,152 words organized in a x32bit configuration. The module consists of eight 1M x 8 FROM mounted on a 72 -pin, double-sided, FR4-printed circuit board.
The HMF2M32M8A is entirely pin and command set compatible with JEDEC standard 4M-bit EEPROMs. Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V flash or EPROM devices.
Eight chip enable inputs, (/1CSLL, /2CSLL, /1CSLH, /2CSLH, /1CSHL, /2CSHL, /1CSHH, /2CSHH ) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output.
When FROM module is disable condition the module is becoming power standby mode, system designer can get low -power design. All module components may be powered from a single +5V DC power supply and all inputs and outputs are TTL-compatible.

FEATURES
*Access time : 75, 90 and 120ns
*High-density 8MByte design
*High-reliability, low-power design
*Single + 5V ± 0.5V power supply
*Easy memory expansion
*All inputs and outputs are TTL-compatible
*FR4-PCB design
*Low profile 72-pin SIMM
*Minimum 1,000,000 write/erase cycle
*Sectors erase architecture
*Sector group protection
*Temporary sector group unprotection
*The used device is Am29F080B

HMF2M32M8A-75, HMF2M32M8A-90, HMF2M32M8A-120

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GENERAL DESCRIPTION
The HMF2M32M8G is a high-speed flash read only memory (FROM) module containing 2,097,152 words organized in a x32bit configuration. The module consists of eight 1M x 8 FROM mounted on a 72 -pin, double-sided, FR4-printed circuit board.
The HMF2M32M8 is entirely pin and command set compatible with JEDEC standard 4M-bit E2 PROMs. Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V flash or EPROM devices.
Eight chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1, /CE_LL1, /CE_UU2, /CE_UM2, /CE_LM2, /CE_LL2) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output.
When FROM module is disable condition the module is becoming power standby mode, system designer can get low -power design. All module components may be powered from a single +5V DC power supply and all inputs and outputs are TTL - compatible.

FEATURES
*Access time : 75, 90 and 120ns
*High-density 8MByte design
*High-reliability, low-power design
*Single + 5V ± 0.5V power supply
*Easy memory expansion
*All inputs and outputs are TTL-compatible
*FR4-PCB design
*Low profile 72-pin SIMM
*Minimum 1,000,000 write/erase cycle
*Sectors erase architecture
*Sector group protection
*Temporary sector group unprotection
*The used device is Am29F080B

HMF2M32M8G-75, HMF2M32M8G-90, HMF2M32M8G-120

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GENERAL DESCRIPTION
The HSD8M32F4V/VA is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32F4V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
-HSD8M32F4V : Height from bottom to top 11.3mm
-HSD8M32F4VA : Height from bottom to top 7.3mm
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
-Latency (Access from column address)
-Burst length (1, 2, 4, 8 & Full page)
-Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*120pin SMM type FR4-PCB design
*The used device is 4Mx8bit x4Banks SDRAM
*Pin assignment is compatible with
-HSD16M64F8V/VA
-HSD32M64F8V/VA
-HSD8M64F8V/VA

HSD8M32F4VA, HSD8M32F4V-13, HSD8M32F4V-12, HSD8M32F4VA-13

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GENERAL DESCRIPTION
The HSD16M72D18A is a 16M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M72D18A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
-HSD16M72D18A-F/10L : 100MHz (CL=3)
-HSD16M72D18A-F/10 : 100MHz (CL=2)
-HSD16M72D18A-F/12 : 125MHz (CL=3)
-HSD16M72D18A-F/13 : 133MHz (CL=3)
-HSD16M72D18A-F/13H : 133MHz (CL=2)
-F means Auto & Self refresh with Low-Power (3.3V)
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
-Latency (Access from column address)
-Burst length (1, 2, 4, 8 & Full page)
-Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*The used device is 8M x 8bit , 4Banks SDRAM

HSD16M72D18A-13, HSD16M72D18A-13H, HSD16M72D18A-12, HSD16M72D18A-10L

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GENERAL DESCRIPTION
The HMF51232M4V is a high-speed flash read only memory (FROM) module containing 524,288 words organized in a x32bit configuration. The module consists of four 512Kx 8 FROM mounted on a 72-pin, single-sided, FR4-printed circuit board.
Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V flash or EPROM devices.
Four chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1, /CE_LL1) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output.
When FROM module is disable condition, the module is becoming power standby mode, system designer can get low-power design.
All module components may be powered from a single +3V DC power supply and all inputs and outputs are TTL-compatible.

FEATURES
*Access time : 55,70, 90 and 120ns
*High-density 2MByte design
*High-reliability, low-power design
*Single + 3V ± 0.3V power supply
*Easy memory expansion
*All inputs and outputs are TTL- compatible
*FR4-PCB design
*Low profile 72-pin SIMM
*Minimum 1,000,000 write/erase cycle
*Sector erases architecture
*Sector group protection
*Temporary sector group unprotection
*Part Identification HMF51232M4V : Gold Plate Lead

HMF51232M4V-55, HMF51232M4V-70, HMF51232M4V-90, HMF51232M4V-120

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GENERAL DESCRIPTION
The HSD16M72D9A is a 16M x 72 bit Synchronous Dynamic RAM high density memory module. The module consists of nine CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M72D9A is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC
power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
- HSD16M72D9A-F/10L : 100MHz (CL=3)
- HSD16M72D9A-F/10 : 100MHz (CL=2)
- HSD16M72D9A-F/13 : 133MHz (CL=3)
- HSD16M72D9A-F/12 : 125MHz (CL=3)
- F means Auto & Self refresh with Low-Power (3.3V)
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*The used device is 4M x 8bit x 4Banks SDRAM

HMD16M72D9A-13, HMD16M72D9A-12, HMD16M72D9A-10L, HMD16M72D9A-10
HMD16M72D9A-F13, HMD16M72D9A-F12, HMD16M72D9A-F10L, HMD16M72D9A-F10
TAG DRAM, ECC, Module

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GENERAL DESCRIPTION
The HSD16M64F8V/VA is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of eight CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin, double-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M64F8V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
- HSD16M64F8V : Stacking Height ( T = 11.3mm )
- HSD16M64F8VA : Stacking Height ( T = 7.3mm )
*Burst mode operation
*Auto & self refresh capability (4K Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*120pin-SMM type FR4-PCB design
*The used device is 16Mx8bit SRAM
*Pin assignment is compatible with
- HSD8M64F8V
- HSD32M64F8V

HSD16M64F8V-13, HSD16M64F8V-F13, HSD16M64F8V-12, HSD16M64F8V-F12, HSD16M64F8V-10, HSD16M64F8V-F10, HSD16M64F8VA-13, HSD16M64F8VA-F13, HSD16M64F8VA-12, HSD16M64F8VA-F12, HSD16M64F8VA-10, HSD16M64F8VA-F10, HSD8M64F8V, HSD32M64F8V
TAG DRAM

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GENERAL DESCRIPTION
The HSD16M64F8K is a 16M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 120-pin glass-epoxy. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M64F8K is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification HSD16M64F8K : 100MHz (CL=2 & CL=3)
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*The used device is 4M x 8bit x 4Banks SDRAM

HSD16M64F8K-10L

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GENERAL DESCRIPTION
The HSD16M64D16A is a 16M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy.
Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.
The HSD16M64D16A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
* Part Identification
- HSD16M64D16A-F/10L : 100MHz (CL=3)
- HSD16M64D16A-F/10 : 100MHz (CL=2)
- HSD16M64D16A-F/12 : 125MHz (CL=3)
- HSD16M64D16A-F/13 : 133MHz (CL=3)
- F means Auto & Self refresh with Low-Power (3.3V)
* Burst mode operation
* Auto & self refresh capability (4096 Cycles/64ms)
* LVTTL compatible inputs and outputs
* Single 3.3V ±0.3V power supply
* MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
* All inputs are sampled at the positive going edge of the system clock
* The used device is 8M x 8bit x 4Banks SDRAM

HSD16M64D16A-13
HSD16M64D16A-12
HSD16M64D16A-10L

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