DESCRIPTION
 The FUJITSU MB3782 is a PWM-type switching regulator controller, designed with open-collector output for connection to external drive transistors and coils, providing a selection of three types of output voltage: step-up, step-down or inverting (inverting output is available on one circuit only).
The MB3782 features identical oscillator output waveforms to enable completely synchronous operation and prevent the occurrence of low-frequency beat between channels.
Also, the MB3782 features low power dissipation (2.1 mA Typ) and a built-in standby mode (10 mA), making possible the configuration of a wide variety of high-efficiency, stable power supplies, even with the use of battery power.
The MB3782 is an ideal power supply for high-performance portable devices such as video camcorders and cameras.

FEATURES
• Wide voltage range (3.6 V to 18 V)
• Low power dissipation (operating mode: 2.1 mA (Typ), standby mode: 10 mA (Max)
• Wide range of oscillator frequencies, high-frequency capability (1 to 500 kHz)
• On-chip timer-latch type short detection circuit
• On-chip undervoltage lockout circuit
• On-chip 2.50 V reference voltage circuit (1.25 V output available at RT pin)
• Dead time adjustment over full duty cycle range
• On-chip standby mode (power on/off function)

MB3782P
MB3782PF

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DESCRIPTION
The MB39A119 is the N-ch MOS drive of the synchronous rectification type DC/DC converter IC using pulsewidth modulation (PWM) type that can charge Li-ion battery from 1 cell to 4 cells and suitable for down-conversion.
This IC integrates built-in comparator for the voltage detection of the AC adapter and switches the power supply to the AC adapter or battery automatically, enabling supply it to system. In addition, the constant voltage control state detection function is built in, which prevents mis-detecting the full charge. The MB39A119 provides a wide range of power supply voltage and low standby current, high efficiency, making it ideal for use as a built-in charge device in products such as notebook PC.

FEATURES
• High efficiency : 97 % (Max)
• High-frequency operation : 1 MHz (Max)
• Built-in off time control function
• Built-in voltage detection function of AC adapter (ACOK, XACOK terminal)
• Preventing mis-detection for the full charge by the constant voltage control state detection function (CVM terminal)


MB39A119QN

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* OUTLINE
The MB89890 series is a line of single-chip microcontrollers containing a great variety of peripheral functions such as dual clock control systems, 4-stage operating speed controller, DTMF signal generator, timer, PWM timer, serial interface, modem, A/D converter and external interrupt, as well as compact instruction set.

* FEATURES
• F2MC-8L family CPU core
• Dual clock control system
• Maximum memory size: 64 Kbytes
• Minimum execution time: 0.5 ms at 8 MHz
• Interrupt processing time: 4.5 ms at 8 MHz
• I/O ports: Max 85 ports
• 21-bit time-base counter
• 8-bit PWM timer
• DTMF generator
• 8/16-bit timer
• 8-bit serial I/O
• Serial I/O with 1-byte buffer
• A/D converter
• Modem timer (pulse-width counter)
• Modem signal output
• External interrupt: 16 channels
• Power-on reset function
• Low-power consumption modes (subclock mode, watch mode, sleep mode, stop mode)
• CMOS technology

MB89899 MB89P899 MB89PV890 MB89898

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ㅁ FEATURES
• 0.33 mm Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
57-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Eight 4K word and sixty-three 32K word sectors in word mode
Eight 8K byte and sixty-three 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
n GENERAL DESCRIPTION
The MBM29DL32XTD/BD are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These
devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and
5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
MBM29DL32XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two
separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.
In the MBM29DL32XTD/BD, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
The standard MBM29DL32XTD/BD offer access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29DL32XTD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29DL32XTD/BD are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL32XTD/BD are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29DL321TD MBM29DL322BD MBM29DL323TD MBM29DL324BD

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FEATURES
・High Output Power: 34.0dBm(typ.)
・High Linear Gain: 26.0dB(typ.)
・Low VSWR
・Broad Band: 7.1~8.5GHz
・Impedance Matched Zin/Zout = 50Ω
・Small Hermetic Metal-Ceramic Package(VF)

DESCRIPTION
The FMM5057VF is a MMIC amplifier that contains a four-stage amplifier, internally matched, for standard communications band in the 7.1 to 8.5GHz frequency range. Fujitsu’s stringent Quality Assurance Program assures the highest reliability and consistent performance.
TAG Amplifier

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