MB85RS256 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells.
MB85RS256 adopts the Serial Peripheral Interface (SPI).
The MB85RS256 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS256 can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS256 does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS256 takes no wait time.

*Bit configuration : 32,768 words × 8 bits
*Operating power supply voltage : 3.0 V to 3.6 V
*Operating frequency : 15 MHz (Max)
*Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
*Operating temperature range : −20 °C to +85 °C
*Data retention : 10 years (+55 °C)
*High endurance : 10 Billion Read/writes
*Package : 8-pin plastic SOP (FPT-8P-M02)


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The MB39A107 is a DC/DC converter IC suitable for down-conversion, using pulse-width modulation (PWM) charging and enabling output voltage to be set to any desired level from 1 cell to 4 cells.
The MB39A107 adopts output for Nch MOS drive of synchronous rectification type.
The MB39A107 can be used to monitor the current in an AC adapter or battery, as it contains a current amplifier that can set an offset voltage.
It can also be used for applications such as setting the charging voltages for 2 batteries.
The MB39A107 provides a broad power supply voltage range and low standby current as well as high efficiency, making it ideal for use as a built-in charging device in products such as notebook PC.

*Built-in low-current control circuits in two systems (supporting dynamically controlled charging)
*The charge current value can be analog controlled (+INE1 and +INE2 terminal)
*Built-in synchronous rectification system output for Nch MOS FET
*Built-in charge pump for driving high-side Nch MOS, providing 100% on-duty support
*Built-in AC adapter detection function
*Output voltage setting accuracy : 4.2 V ± 0.74 % (Ta = - 10 °C to + 85 °C)
*Built-in high accuracy current detection amplifier : ± 5 % (input voltage difference at 100 mV), ±15 % (input voltage difference at 20 mV)
*Output voltage setting using external resistor : 1 cell to 4 cells
*Oscillation frequency range : 100 kHz to 1 MHz
*In standby mode, leave output voltage setting resistor open to prevent inefficient current loss.
*Built-in standby current function : 0 mA (Typ)
*Built-in soft-start function independent of loads


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The Fujitsu MB15F86UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.
The Fractional-N PLL operating up to 2500* MHz and the integer PLL operating up to 600 MHz are integrated on one chip.
The MB15F86UL is used, as charge pump which is well-balanced output current with 1.5 mA and 6 mA selectable by serial data, direct power save control and digital lock detector. In addition, the MB15F86UL adopts a new architecture to achieve fast lock.
The new package (Thin Bump Chip Carrier20) decreases a mount area of MB15F86UL more than 30% comparing with the former B.C.C.16 (for dual PLL, MB15F03SL) .
The MB15F86UL is ideally suited for wireless mobile communications, such as TDMA or CDMA.

*High frequency operation : RF synthesizer : 2500* MHz Max, IF synthesizer : 600 MHz Max
*Low power supply voltage : VCC = 2.7 V to 3.6 V
*Ultra Low power supply current : ICC = 5.8 mA Typ (VCC = Vp = 3.0 V, Ta = +25 °C, SW = 0 in IF and RF locking state)
*Direct power saving function : Power supply current in power saving mode Typ 0.1 mA (VCC = Vp = 3.0 V, Ta = +25 °C) , Max 10 mA (VCC = Vp = 3.0 V)
*Fractional function : modulo 3 to 16 programmable (implemented in RF-PLL)
*Dual modulus prescaler : 2500* MHz prescaler (16/17 or 32/33) /600 MHz prescaler (8/9 or 16/17)
*Serial input 14-bit programmable reference divider : R = (RF section 8 bit) 3 to 255, (IF section 14 bit) 3 to 16, 383
*Serial input programmable divider consisting of :
RF section- Binary 5-bit swallow counter : 0 to 31
-Binary 10-bit programmable counter : 18 to 1,023
-Binary 4-bit fractional counter numerator : 0 to 15
IF section - Binary 4-bit swallow counter : 0 to 15
-Binary 11-bit programmable counter : 3 to 2,047
*On-chip phase comparator for fast lock and low noise
*Operating temperature : Ta = -40 °C to +85 °C
*Small package Bump Chip Carrier.0 (3.4 mm ´ 3.6 mm ´ 0.6 mm)


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The Fujitsu Microelectronics MB88346L is a 12-channel 8-bit D/A converter capable of low-voltage operation that has amplifiers built into each of the 12 analog output lines to deliver heavy-current drive capability.
The use of serial data input means that only three control lines are required, and enables cascade connection of multiple MB88346L chips.
The MB88346L is suitable for applications such as electronic volume controls and replacing trimmer potentiometers in tuning systems. In addition, the MB88346L is both function-compatible and pin-compatible the currently used MB88346B, making it easy to reduce the voltage level of a system by simply replacing the MB88346B with the MB88346L.

*Low voltage operation (VCC/VDD : 2.7 V to 3.6 V)
*Ultra-low power consumption (0.5 mW/ch at VCC = 3 V)
*Ultra-compact space-saving package lineup (SSOP-20)
*Contains 12-channel R-2R type 8-bit D/A converter
*On-chip analog output amps (sink current max. 1.0 mA, source current max. 1.0 mA)
*Analog output range from 0 to VCC
*Two separate power supply/ground lines for MCU interface block/operational amplifier output buffer block and D/A converter block
*Serial data input : maximum operating speed 2.5 MHz
(maximum operating speed in cascade connection is 1.5 MHz)
*CMOS process
*Package lineup includes DIP 20-pin, SSOP 20-pin

MB88346LP, MB88346LPFV

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MB88154 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency.

*Input frequency : 16.6 MHz to 67 MHz
*Output frequency: 16.6 MHz to 67 MHz (One time input frequency)
*Modulation rate can select from ± 0.5%, ± 1.0%, ± 1.5% or − 1.0%, − 2.0%, − 3.0%. (For center spread / down spread.)
*Equipped with crystal oscillation circuit: Range of oscillation 16.6 M MHz to 48 MHz
*The external clock can be input: 16.6 MHz to 67 MHz
*Modulation clock output Duty : 40% to 60%
*Modulation clock Cycle-Cycle Jitter : Less than 100 ps
*Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load)
*Power supply voltage : 3.3 V ± 0.3 V
*Operating temperature : − 40 °C to +85 °C
*Package : SOP 8-pin

MB88154-102, MB88154-103, MB88154-112, MB88154-113

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The MB39A104 is a 2-channel DC/DC converter IC using pulse width modulation (PWM), incorporating an overcurrent protection circuit (requiring no current sense resistor). This IC is ideal for down conversion.
Operating at high frequency reduces the value of coil.
This is ideal for built-in power supply such as LCD monitors and ADSL.
This product is covered by US Patent Number 6,147,477.

*Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
*Power supply voltage range : 7 V to 19 V
*Reference voltage : 5.0 V ± 1 %
*Error amplifier threshold voltage : 1.24 V ± 1 %
*High-frequency operation capability : 1.5 MHz (Max)
*Built-in standby function: 0 μA (Typ)
*Built-in soft-start circuit independent of loads
*Built-in totem-pole type output for P-ch MOS FET
*One type of package (SSOP-24 pin : 1 type)

*LCD monitor/panel
*IP phone
*Video capture etc.


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CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.

*Technology :
- 90 nm Si gate CMOS
- 6- to 10-metal layers.
- Low-K (low permittivity) material is used for all dielectric inter-layers.
- Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip.
- The design rules comply with industry standard processes.
*Power supply voltage : + 0.9 V to + 1.3 V (A wide range is supported.)
*Operation junction temperature : − 40 °C to + 125 °C (standard)
*Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
*Gate power consumption : 2.7 nW/gate (1.2 V, 2 NAND, F/O = 1, operating rate 0.5) , 1.8 nW/gate (1.0 V, 2 NAND, F/O = 1, operating rate 0.5)
*High level of integration : Up to 91 million gates
*Reduced chip sized realized by I/O with pad.
*Two types of library sets are supported. (Performance focused (1.2 V) , Low power consumption supported (0.9 V to 1.3 V) )
*Low power consumption design (multi-power supply design and power gating) is supported.
*Compliance with industry standard design rules enables non-Fujitsu Microelectronics commercial macros to be easily incorporated.
*Compiled cell (RAM, ROM, others)
*Support for ultra high speed (up to 10 Gbps) interface macros.
*Special interfaces (LVDS, SSTL2, others)
*Supports use of industry standard libraries (.LIB).
*Uses industry standard tools and supports the optimum tools for the application.
*Short-term development using a physical prototyping tool
*One pass design using a physical synthesis tool
*Hierarchical design environment for supporting large-scale circuits
*Support for Signal Integrity, EMI noise reduction
*Support for static timing sign-off
*Optimum package range : FBGA, FC-BGA, PBGA,TEBGA

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-High Speed Switching
-Low On-Resistance
-No Secondary Breakdown
-Low Driving Power
-High Voltage
-VGS = ± 30V Guarantee
-Repetitive Avalanche Rated

-Switching Regulators
-DC-DC converters
-General Purpose Power Amplifier


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The MB85R2001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words × 8 bits of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.
The MB85R2001 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R2001 can be used for at least 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM.
The MB85R2001 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.

* Bit configuration : 262,144 words × 8 bits
* Read/write endurance : 1010 times/bit (Min)
* Operating power supply voltage : 3.0 V to 3.6 V
* Operating temperature range : − 20 °C to + 85 °C
* Data retention : 10 years ( + 55 °C)
* Package : 48-pin plastic TSOP (1)


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 The MB95120MB series is general-purpose, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.

* F2MC-8FX CPU core Instruction set optimized for controllers
- Multiplication and division instructions
- 16-bit arithmetic operations
- Bit test branch instruction
- Bit manipulation instructions etc.
* Clock
- Main clock
- Main PLL clock
- Sub clock
- Sub PLL clock
* Timer
- 8/16-bit compound timer × 2 channels
- Can be used to interval timer, PWC timer, PWM timer and input capture.
- 16-bit reload timer × 1 channel
- 8/16-bit PPG × 2 channels
- 16-bit PPG × 2 channels
- Timebase timer × 1 channel
- Watch prescaler × 1 channel
* LIN-UART × 1 channel
- LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
- Full duplex double buffer
* UART/SIO × 1 channel
- Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
- Full duplex double buffer
* I2C* × 1 channel
- Built-in wake-up function
* External interrupt × 12 channels
- Interrupt by edge detection (rising, falling, or both edges can be selected)
- Can be used to recover from low-power consumption (standby) modes.
* 8/10-bit A/D converter × 12 channels
- 8-bit or 10-bit resolution can be selected
* LCD controller (LCDC)
- 40 SEG × 4 COM (Max 160 pixels)
- With blinking function
* Low-power consumption (standby) mode
- Stop mode
- Sleep mode
- Watch mode
- Timebase timer mode
* I/O port
- The number of maximum ports : Max 87
- Port configuration
- General-purpose I/O ports (N-ch open drain) : 2 ports
- General-purpose I/O ports (CMOS) : 85 ports
* Programmable input voltage levels of port
  Automotive input level / CMOS input level / hysteresis input level
* Dual operation Flash memory
- Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
* Flash memory security function Protects the content of Flash memory (Flash memory device only)


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