Description
The EP3102 is a monolithic integrated circuit that provide all the active functions for a step-down switching regulator, capable of driving a 2A load without additional transistor component. Requiring a minimum number of external component, the board space can be saved easily. The external shutdown function can be controlled by TTL logic level and then come into standby mode. The internal compensation makes feedback control have good line and load regulation without external design. Regarding protected function, thermal shutdown is to prevent over temperature operating from damage, and current limit is against over current operating of the output switch. The EP3102 operates at a switching frequency of 150KHz thus allowing smaller sized filter components than what would be needed with lower frequency switching regulators. Other features include a guaranteed +4% tolerance on output voltage under specified input voltage and output load conditions, and +15% on the oscillator frequency. The output version included fixed 3.3V, 5V, 12V, and an adjustable type. The package is available in a standard 8-lead SOP8.

Features
*3.3V, 5V, 12V and Adjustable Output Version
*Adjustable Version Output Voltage Range, 1.23V to 37V +4% Max over Line and Load Condition
*Input Voltage Range up to 40V
*Output Load Current: 2A
*150 KHz Fixed Frequency Internal Oscillator
*Voltage Mode Non-synchronous PWM Control
*Thermal-shutdown and Current-limit Protection
*ON/OFF Shutdown Control Input
*Low Power Standby Mode
*Built-in Switching Transistor on Chip
*SOP-8L package

Applications
*Simple High-efficiency Step-down (Buck) Regulator
*Efficient Pre-regulator for Linear Regulators
*On-card Switching Regulators
*Positive to Negative Converter
*Battery Charger

EP3102-S33R, EP3102-S50R, EP3102-S12R, EP3102-SR

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Description
The EP1117 is a low dropout three-terminal adjustable or fixed-voltage regulator with 1A output current capability. The EP1117 is available in an adjustable version, with output ranging from 1.25V to 10.7V and fixed output voltages of 1.8V, 2.5V, 3.3V and 5.0V. Dropout voltage is guaranteed at a maximum of 1.3V at 1A. On-chip thermal limiting provides protection against any combination of overload that would create excessive junction temperatures. The EP1117 is available in the industry standard 3-pin the low profile surface mount SOT-223 and TO-252 power packages.

Features
*Guaranteed Output Voltage Accuracy within 2%
*Fast Transient Response
*Load Regulation: 0.1% Typ.
*Line Regulation: 0.03% Typ.
*Low Dropout Voltage: 1.1V Typ. at IOUT =1A
*On-chip Thermal Limiting: 150°C Typ.
*Adjustable Output: 1.25~10.7V
*Standard 3-pin SOT-223 and TO252 Power Packages

Applications
*PC peripheral
*Low Voltage Logic Supplies
*Post Regulator for Switching Power Supply

EP1117-F18R, EP1117-D18R, EP1117-F25R, EP1117-D25R

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Description
The EM484M3244VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 1Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.
The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL.
Available packages:TSOPII 86P 400mil.

Features
*Fully Synchronous to Positive Clock Edge
*Single 3.3V ±0.3V Power Supply
*LVTTL Compatible with Multiplexed Address
*Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page
*Programmable CAS Latency (C/L) - 2 or 3
*Data Mask (DQM) for Read / Write Masking
*Programmable Wrap Sequence
-Sequential (B/L = 1/2/4/8/full Page)
-Interleave (B/L = 1/2/4/8)
*Burst Read with Single-bit Write Operation
*All Inputs are Sampled at the Rising Edge of the System Clock
*Auto Refresh and Self Refresh
*4,096 Refresh Cycles / 64ms (15.625us)

EM484M3244VTA-75F, EM484M3244VTA-7F, EM484M3244VTA-6F

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DESCRIPTION
The EP1551 is a small, high efficiency, five-channel, power-supply for digital still and video cameras. It consists of:
*Step-up DC-DC converter with on-chip power MOSFETs for 3.3V main system supply with up to 95% efficiency. It accepts inputs from 0.7V to 5.5V and regulates a resistor-adjustable output from 2.7V to 5.5V.
*Step-down main DC-DC converter with on-chip power MOSFETs for 1.5V DSP core supply with up to 92% efficiency. It can operate from the Step-up main system supply providing buck-boost capability with up to 90% compound efficiency, or it can run directly from battery if buck-boost operation is not needed.
*PWM controller with external FET for Step-up DC-DC converter for 5V motor actuator
*PWM controller with external FET for 15V LCD supply
*PWM controller with external FET and transformer for –7.5V and +15V CCD Bias
All DC-DC channels operate at one fixed frequency settable from 100KHz to 1MHz to optimize size, cost and efficiency. Other features include soft-start, power-OK outputs, and overload protection. The EP1551 is available in apace saving QFN-32 5 x 5 mm packages. An evaluation kit is also available to expedite design.

FEATURES
*Up to 95% efficiency Step-up and up to 92% efficient Step-down converters
*Combine Step-up and Step-down for up to 87% efficiency buck-boost operations
*Minimum 0.7V input voltage
*2μA shutdown mode
*Internal soft start control
*Overload protection
*Compact QFN-32 5 x 5 mm package

APPLICATIONS
*Digital still camera
*Digital video camera
*PDA
*MP3
*PMP
*Portable DVD Player
*Car navigation
TAG Power, Supply

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Description
The EU101x is an OTP type 8-bit micro-controller with 2(EU1010)/4(EU1011) channels of 10-bit A/D converter using advanced CMOS process. The EU101x is specially designed for various industrial field applications. The EU101x incorporates two sets of 8-bit timer/counters, where timer0/1 is specially designed for PWM (Pulse Width Modulation) generator. There are 8 I/O ports and 12 I/O ports with EU1010 and EU1011, respectively. Considering form factor and manufacturability, the EU1010 is packaged into 10-pin non-JEDEC-standard compact-size SOP while the EU1011 is packaged into 14-pin non-JEDEC-standard compact-size SOP.

Features
*2.2V to 5.5V Input Voltage Range
*8 I/O ports in EU1010
*12 I/O ports in EU1011
*RAM size: 128 x 8 bits
*The STACK RAM is included.
*Program ROM size: 4K x 8 bits OTP
*10 bits A/D Converter input source.
-EU1010: 2 channels
-EU1011: 4 channels
*One set of 16-bit down count timer and one set of 8-bit timer.
*Operating temperature: -40 ~ +85 ℃
*Build-in Low Voltage Reset (LVR) circuit.
*Oscillator: Internal RC oscillation.

EU1011, EU1010-XX-SUR, EU1011-XX-SUR, EU1010-XX-SUT, EU1011-XX-SUT
TAG A/D, Converter, MCU

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Description
The EP3101 series are monolithic integrated circuits that provide all the active functions for a step-down DC/DC converter, capable of driving a 3A load without additional transistor component. Requiring a minimum number of external components, the board space can be saved easily. The external shutdown function can be controlled by TTL logic level and then come into standby mode. The internal compensation makes feedback control have good line and load regulation without external design. Regarding protected function, thermal shutdown is to prevent over temperature operating from damage, and current limit is against over current operating of the output switch.
The EP3101 series operates at a switching frequency of 150KHz thus allowing smaller sized filter frequency switching regulators. Other features include a guaranteed ±4% tolerance on output voltage under specified input voltage and output load conditions, and ±15 % on the oscillator frequency. The output version includes fixes 3.3V, 5V, 12V, and an adjustable type. The packages are available in a standard 5-lead TO-220(T) package and a 5-lead TO-263(U)..

Features
*Output Voltage: 3.3V, 5V, 12V and Adjustable Output Version
*Adjustable Version Output Voltage Range, 1.23V to 37V ±4%
*150KHz±15% Fixed Switching Frequency
*Voltage Mode Asynchronous PWM Control
*Thermal-shutdown and Current-limit Protection
*ON/OFF Shutdown Control Input
*Operating Voltage can be up to 40V
*Output Load Current: 3A
*Low Power Standby Mode
*Built-in on Chip Switching Transistor
*TO263-5L and TO220-5L Packages

Applications
*Simple High-efficiency Step-down Regulator
*On-card Switching Regulators
*Positive to Negative Converter

EP3101-X33R, EP3101-X50R, EP3101-X12R, EP3101-XR

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Description
The EM44AM1684LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

Features
*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBA-5F, EM44AM1684LBA-37F, EM44AM1684LBA-3F

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Description
The EM44AM1684LBC is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

Features
*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBC-5F, EM44AM1684LBC-37F, EM44AM1684LBC-3F

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Description
The EM488M3244LBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.
The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.
Available packages: TFBGA-90B(13mmx8mm).

Features
*Fully Synchronous to Positive Clock Edge
*Single 1.8V ±0.1V Power Supply
*LVCMOS Compatible with Multiplexed Address
*Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page
*Programmable CAS Latency (C/L) - 2 or 3
*Data Mask (DQM) for Read / Write Masking
*Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
*Burst Read with Single-bit Write Operation
*All Inputs are Sampled at the Rising Edge of the System Clock
*Auto Refresh and Self Refresh
*4,096 Refresh Cycles / 64ms (15.625us)
*Programmable Driver Strength Control
–1/2, 1/4 of Full Strength

EM481M3244LBA-7FE, EM482M3244LBA-7FE, EM484M3244LBA-7FE, EM488M3244LBA-7FE, EM48AM3244LBA-7FE, EM48BM3244LBA-7FE, EM481M3244LBA-75FE, EM482M3244LBA-75FE, EM484M3244LBA-75FE, EM488M3244LBA-75FE, EM48AM3244LBA-75FE, EM48BM3244LBA-75FE, EM481M3244LBA-8FE, EM482M3244LBA-8FE, EM484M3244LBA-8FE, EM488M3244LBA-8FE, EM48AM3244LBA-8FE, EM48BM3244LBA-8FE

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Description
The EM488M1644VBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 16 bits.
All inputs and outputs are synchronized with the positive edge of the clock.
The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system.
It also provides auto refresh with power saving / down mode.
All inputs and outputs voltage levels are compatible with LVTTL.
Available packages:TFBGA-54B(8mmx8mm).

Features
* Fully Synchronous to Positive Clock Edge
* Single 2.75V ~ 3.6V Power Supply
* LVTTL Compatible with Multiplexed Address
* Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page
* Programmable CAS Latency (C/L) - 2 or 3
* Data Mask (DQM) for Read / Write Masking
* Programmable Wrap Sequence
- Sequential (B/L = 1/2/4/8/full Page)
- Interleave (B/L = 1/2/4/8)
* Burst Read with Single-bit Write Operation
* All Inputs are Sampled at the Rising Edge of the System Clock
* Auto Refresh and Self Refresh
* 4,096 Refresh Cycles / 64ms (15.625us)

EM488M1644VBB-75F
EM488M1644VBB-7F
TAG DRAM

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