Description
The HB54A5129F1U is a 64M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 18 pieces of 256Mbits DDR SDRAM (HM5425401BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
*184-pin socket type package (dual lead out)
-Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness)
-Lead pitch: 1.27mm
*2.5V power supply (VCC/VCCQ)
*SSTL-2 interface for all inputs and outputs
*Clock frequency: 143MHz/133MHz/125MHz (max.)
*Data inputs and outputs are synchronized with DQS
*4 banks can operate simultaneously and independently (Component)
*Burst read/write operation
*Programmable burst length: 2, 4, 8
-Burst read stop capability
*Programmable burst sequence
-Sequential
-Interleave
*Start addressing capability
-Even and Odd
*Programmable /CAS latency (CL): 3, 3.5
*8192 refresh cycles: 7.8μs (8192/64ms)
*2 variations of refresh
-Auto refresh
-Self refresh
HB54A5129F1U-A75B, HB54A5129F1U-B75B, HB54A5129F1U-10B
Description
The EBE21RD4ABHA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board.
Features
*240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free
*1.8V power supply
*Data rate: 533Mbps/400Mbps (max.)
*1.8 V (SSTL_18 compatible) I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in
capturing data at the receiver
*DQS is edge aligned with data for READs; center aligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data referenced to both edges of DQS
*Four internal banks for concurrent operation (Components)
*Burst length: 4, 8
*/CAS latency (CL): 3, 4, 5
*Auto precharge option for each burst access
*Auto refresh and self refresh modes
*7.8μs average periodic refresh interval
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
*1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)
EBE21RD4ABHA-5C-E, EBE21RD4ABHA-4A-E
Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
Features
*3.3 V Power supply
*Clock frequency: 100 MHz/83 MHz
*LVTTL interface
*Single pulsed RAS
*2 Banks can operates simultaneously and independently
*Burst read/write operation and burst read/single write operation capability
*Programmable burst length: 1/2/4/8/full page
*2 variations of burst sequence
-Sequential (BL = 1/2/4/8/full page)
-Interleave (BL = 1/2/4/8)
*Programmable CAS latency: 1/2/3
*Byte control by DQMU and DQML
*Refresh cycles: 4096 refresh cycles/64 ms
*2 variations of refresh
-Auto refresh
-Self refresh
HM5216165TT-10H, HM5216165TT-12
Description
The EBE51UD8AEFA is 64M words × 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA (μBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4 bits prefetchpipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (μBGA) on the module board.
Features
*240-pin socket type dual in line memory module (DIMM)
- PCB height: 30.0mm
- Lead pitch: 1.0mm
- Lead-free
*Power supply: VDD = 1.8V ± 0.1V
*Data rate: 667Mbps (max.)
*SSTL_18 compatible I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used capturing data at the receiver
*DQS is edge aligned with data for READs: centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS
*Four internal banks for concurrent operation (components)
*Data mask (DM) for write data
*Burst lengths: 4, 8
*/CAS Latency (CL): 3, 4, 5
*Auto precharge operation for each burst access
*Auto refresh and self refresh modes
*Average refresh period
- 7.8μs at 0°C ≤ TC ≤ +85°C
- 3.9μs at +85°C < TC ≤ +95°C
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
EBE51UD8AEFA-6E-E
Specifications
*Density: 512M bits
*Organization
- 16M words × 8 bits × 4 banks (EDD5108AGTA)
- 8M words × 16 bits × 4 banks (EDD5116AGTA)
*Package: 66-pin plastic TSOP (II)
- Lead-free (RoHS compliant)
*Power supply: VDD, VDDQ = 2.5V ± 0.2V
*Data rate: 400Mbps/333Mbps/266Mbps (max.)
*Four internal banks for concurrent operation
*Interface: SSTL_2
*Burst lengths (BL): 2, 4, 8
*Burst type (BT):
- Sequential (2, 4, 8)
- Interleave (2, 4, 8)
*/CAS Latency (CL): 2, 2.5, 3
*Precharge: auto precharge option for each burst access
*Driver strength: normal/weak
*Refresh: auto-refresh, self-refresh
*Refresh cycles: 8192 cycles/64ms
- Average refresh period: 7.8μs
*Operating ambient temperature range
- TA = 0°C to +70°C
Features
*Double-data-rate architecture; two data transfers per clock cycle
*The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
*Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
*Data inputs, outputs, and DM are synchronized with DQS
*DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
*Data mask (DM) for write data
DDR400B, DDR400C, DDR333B, DDR266A, DDR266B
Specifications
* Density: 128M bits
* Organization
- 2M words × 16 bits × 4 banks
* Package: 54-pin plastic TSOP (II)
- Lead-free (RoHS compliant)
* Power supply: VDD, VDDQ = 3.3V ± 0.3V
* Clock frequency: 166MHz/133MHz (max.)
* Four internal banks for concurrent operation
* Interface: LVTTL
* Burst lengths (BL): 1, 2, 4, 8, full page
* Burst type (BT):
- Sequential (1, 2, 4, 8, full page)
- Interleave (1, 2, 4, 8)
* /CAS Latency (CL): 2, 3
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 4096 cycles/64ms
- Average refresh period: 15.6μs
* Operating ambient temperature range
- TA = 0°C to +70°C
Features
* Single pulsed /RAS
* Burst read/write operation and burst read/single write operation capability
* Byte control by UDQM and LDQM
Specifications
* Density: 1GB
* Organization
- 128M words × 72 bits, 1 rank
* Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA
* Package: 240-pin socket type dual in line memory module (DIMM)
- PCB height: 30.0mm
- Lead pitch: 1.0mm
- Lead-free (RoHS compliant)
* Power supply: VDD = 1.8V ± 0.1V
* Data rate: 667Mbps/533Mbps/400Mbps (max.)
* Four internal banks for concurrent operation (components)
* Interface: SSTL_18
* Burst lengths (BL): 4, 8
* /CAS Latency (CL): 3, 4, 5
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 8192 cycles/64ms
- Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
* Operating case temperature range
- TC = 0°C to +95°C
Features
* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
* DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transitions with CK transitions
* Commands entered on each positive CK edge; data referenced to both edges of DQS
* Posted /CAS by programmable additive latency for better command and data bus efficiency
* Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
* /DQS can be disabled for single-ended Data Strobe operation
* 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2K bits EEPROM) for Presence Detect (PD)
EBE10RD4AJFA-6E-E
EBE10RD4AJFA-5C-E
EBE10RD4AJFA-4A-E
Specifications
* Density: 512MB
* Organization
- 64M words × 72 bits, 1 rank
* Mounting 9 pieces of 512M bits DDR2 SDRAM sealed in FBGA
* Package
- 240-pin fully buffered, socket type dual in line memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
- Advanced Memory Buffer (AMB): 655-ball FCBGA
- Lead-free (RoHS compliant)
* Power supply
- DDR2 SDRAM: VDD = 1.8V ± 0.1V
- AMB: VCC = 1.5V + 0.075V/−0.045
* Data rate: 667Mbps/533Mbps (max.)
* Four internal banks for concurrent operation (components)
* Interface: SSTL_18
* Burst lengths (BL): 4, 8
* /CAS Latency (CL): 3, 4, 5
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 8192 cycles/64ms
- Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
* Operating case temperature range
- TC = 0°C to +95°C
Features
* JEDEC standard Raw Card A Design
* Industry Standard Advanced Memory Buffer (AMB)
* High-speed differential point-to-point link interface at 1.5V (JEDEC draft spec)
- 14 north-bound (NB) high speed serial lanes
- 10 south-bound (SB) high speed serial lanes
* Various features/modes:
- MemBIST and IBIST test functions
- Transparent mode and direct access mode for DRAM testing
- Interface for a thermal sensor and status indicator
* Channel error detection and reporting
* Automatic DDR2 SDRAM bus and channel calibration
* SPD (serial presence detect) with 1piece of 256 byte serial EEPROM
EBE51FD8AGFD-6E-E
EBE51FD8AGFD-5C-E
EBE51FD8AGFN-6E-E
EBE51FD8AGFN-5C-E
