FUNCTIONAL DESCRIPTION
The DLO31F-series device is a gated delay line oscillator. The device produces a stable square wave which is synchronized with the falling edge of the Gate Input (GB). The frequency of oscillation is given by the device dash number (See Table). The two outputs (C1,C2) are in phase during oscillation, but return to opposite logic levels when the device is disabled.

FEATURES
*Continuous or keyable wave train
*Synchronizes with arbitrary gating signal
*Fits standard 14-pin DIP socket
*Low profile
*Auto-insertable
*Input & outputs fully TTL interfaced & buffered
*Available in frequencies from 2MHz to 40MHz

DLO31F-2, DLO31F-2.5, DLO31F-3, DLO31F-3.5, DLO31F-4, DLO31F-4.5

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FUNCTIONAL DESCRIPTION
The 3D7418 Programmable 8-Bit Silicon Delay Line product family consists of 8-bit, user-programmable CMOS silicon integrated circuits. Delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps ranging from 250ps to 5.0ns inclusively. Units have a typical inherent (zero step) delay of 12ns to 17ns (See Table 1). The input is reproduced at the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Increment range: 0.25 through 5.0ns
*Delay tolerance: 1% (See Table 1)
*Temperature stability: ±3% typical (0C-70C)
*Vdd stability: ±1% typical (4.75V-5.25V)
*Minimum input pulse width: 10% of total delay
*Programmable via 3-wire serial or 8-bit parallel interface

3D7418-0.25, 3D7418-0.5, 3D7418-1, 3D7418-2, 3D7418-3, 3D7418-4, 3D7418-5

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FUNCTIONAL DESCRIPTION
The 1518-series device is a fixed, single-input, fiveoutput, passive delay line. The signal input (IN) is reproduced at the outputs (T1-T5) in equal increments. The delay from IN to T5 (TD) and the characteristic impedance of the line (Z) are determined by the dash number. The rise time (TR) of the line is 30% of TD, and the 3dB bandwidth is given by 1.05 / TD. The device is available in a 14-pin SMD with two pinout options.
Part numbers are constructed according to the scheme shown at right. For example, 1518-101-500A is a 100ns, 50W delay line with pinout code A. Similarly, 1518-151-501 a is 150ns, 500W delay line with standard pinout.

FEATURES
*5 taps of equal delay increment
*Delays to 200ns
*Low profile
*Epoxy encapsulated
*Meets or exceeds MIL-D-23859C

1518-5-10IN, 1518-10-10IN, 1518-15-10IN, 1518-100-10IN, 1518-200-10IN
TAG DELAY, line, SMD

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FUNCTIONAL DESCRIPTION
The 3D3424 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by:
TDn = T0 + An * TI
where T0 is the inherent delay, An is the delay address of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC.

FEATURES
*Four indep’t programmable lines on a single chip
*All-silicon CMOS technology
*Low quiescent current (5mA typical)
*Leading- and trailing-edge accuracy
*Vapor phase, IR and wave solderable
*Increment range: 1ns through 300ns
*Delay tolerance: 3% or 2ns (see Table 1)
*Line-to-line matching: 1% or 1ns typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*Minimum input pulse width: 10% of total delay

3D3424-1, 3D3424-1.5, 3D3424-2, 3D3424-4, 3D3424-5, 3D3424-10, 3D3424-15
3D3424-20, 3D3424-40, 3D3424-50, 3D3424-100, 3D3424-200, 3D3424-300

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FUNCTIONAL DESCRIPTION
The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 6ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D7323 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7323 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Delay range: 6 through 6000ns
*Delay tolerance: 2% or 1.0ns
*Temperature stability: ±3% typ (-40C to 85C)
*Vdd stability: ±1% typical (4.75V to 5.25V)
* Minimum input pulse width: 20% of total delay
*14-pin DIP available as drop-in replacement for hybrid delay lines

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DESCRIPTION
The 3D3701 Delay Line Oscillator product family consists of fixed-frequency CMOS integrated circuit oscillators. Each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. The device frequency can range from 0.3MHz through 100MHz. The 3D3701 has two outputs that are in phase when the oscillator is running. The 3D3701 is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC package.

FEATURES
*All-silicon, low-power CMOS technology
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Frequency range: 0.3MHz through 100MHz
*Frequency tolerance: 0.5% typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*14-pin DIP available as drop-in replacements for hybrid delay line oscillators

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FUNCTIONAL DESCRIPTION
The DDU39F-series device is a mechanically variable, FAST-TTL interfaced delay line.
The signal input (IN) is reproduced at the tap output (OUT), shifted by an amount which can be adjusted between 7ns and 25ns.
The device operates from a single 5V supply and is TTL interfaced, capable of driving up to 10 TTL loads.

FEATURES
*Ideal for “Set and Forget” applications
*Multi-turn adjustment screw (approx. 15 turns)
*Fits standard 16-pin DIP socket
*Input & output fully TTL interfaced & buffered (10 T2L fan-out capability)
*Resolution: 0.5ns typical
*Adjustment range: 7ns to 25ns
*Output rise time: 4ns typical
*Min. input pulse width: 10ns
*Power dissipation: 230mW maximum
*Operating temperature: 0° to 70°C (Commercial) -55° to 125°C (Military)

APPLICATION NOTES
*HIGH FREQUENCY RESPONSE
The DDU39F tolerances are guaranteed for input pulse widths and periods greater than those
specified in the test conditions.
Although the device will function properly for pulse widths as small as 10ns and periods as small 20ns (for a symmetric input), the delays may deviate from their values at low frequency.
However, for a given input condition, the deviation will be repeatable from pulse to pulse.
Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.
*POWER SUPPLY BYPASSING
The DDU39F relies on a stable power supply to produce repeatable delays within the stated
tolerances.
A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended.
A wide VCC trace and a clean ground plane should be used.

DDU39F
DDU39FM
TAG TTL

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FUNCTIONAL DESCRIPTION
The 3D7521 is a monolithic CMOS Manchester Encoder.
The clock and data, present at the unit input, are combined into a single bi-phase-level signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ).
All pins marked N/C must be left unconnected.
The all-CMOS 3D7521 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.
The 3D7521 Manchester Encoder samples the data input at the rising edge of the input clock.
The sampled data is used in conjunction with the clock rising and falling edges to generate the by-phase level Manchester code.

FEATURES
* All-silicon, low-power CMOS technology
* TTL/CMOS compatible inputs and outputs
* Vapor phase, IR and wave solderable
* Low ground bounce noise
* Maximum data rate: 50 MBaud

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FUNCTIONAL DESCRIPTION
 The 3D7522 product family consists of monolithic CMOS Manchester Decoders.
The unit accepts at the RX input a bi-phase-level, embedded-clock signal.
In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted.
The operating baud rate (in MBaud) is specified by the dash number.
The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.
Because the 3D7522 is not PLL-based, it does not require a long preamble in order to lock onto the received signal.
Rather, the device requires at most one bit cell before the data presented at the output is valid.
This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.
The all-CMOS 3D7522 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.

FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Low ground bounce noise
• Maximum data rate: 50 MBaud
• Data rate range: ±15%
• Lock-in time: 1 bit

3D7522-0.5
3D7522-1
3D7522-5
3D7522-10
3D7522-20
3D7522-25
3D7522-50

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FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 0.75ns through 7000ns
• Delay tolerance: 2% or 0.5ns
• Temperature stability: ±2% typical (-40C to 85C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Minimum input pulse width: 15% of total delay
• 14-pin Gull-Wing available as drop-in replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION
 The 3D3220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number.
 
 The 3D3220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. The all-CMOS 3D3220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.

APPLICATION NOTES
OPERATIONAL DESCRIPTION The 3D3220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

 To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D3220 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH
 The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

 To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D3220 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

3D3220-xx
3D3220G-XX
3D3220D-xx
3D3220S-xx

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