Functional Description
The Cypress STK15C88 is a 256Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
PowerStore nvSRAM products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. If the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88 for more reliable operation.

Features
*25 ns and 45 ns access times
*Pin compatible with industry standard SRAMs
*Automatic nonvolatile STORE on power loss
*Nonvolatile STORE under Software control
*Automatic RECALL to SRAM on power up
*Unlimited Read/Write endurance
*Unlimited RECALL cycles
*1,000,000 STORE cycles
*100 year data retention
*Single 5V+10% power supply
*Commercial and Industrial Temperatures
*28-pin (300 mil and 330 mil) SOIC packages
*RoHS compliance

STK15C88-NF25TR, STK15C88-NF25, STK15C88-NF45TR, STK15C88-NF45

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Description
The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM (nvSRAM) with a full featured real time clock in a reliable, monolithic integrated circuit.
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.
The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control.

Features
*nvSRAM Combined with Integrated Real Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor)
*Capacitor or Battery Backup for RTC
*25, 45 ns Read Access and Read/Write Cycle Time
*Unlimited Read/Write Endurance
*Automatic nonvolatile STORE on Power Loss
*Nonvolatile STORE Under Hardware or Software Control
*Automatic RECALL to SRAM on Power Up
*Unlimited RECALL Cycles
*200K STORE Cycles
*20-Year nonvolatile Data Retention
*Single 3 V +20%, -10% Power Supply
*Commercial and Industrial Temperatures
*48-pin 300-mil SSOP Package (RoHS-Compliant)

STK17TA8-RF25, STK17TA8-RF45, STK17TA8-RF25TR, STK17TA8-RF45TR
TAG Clock, nvsram

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Description
The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.

Features
*2.5V or 3.3V operation
*200-MHz clock support
*LVPECL or LVCMOS/LVTTL clock input
*LVCMOS/LVTTL compatible outputs
*15 clock outputs: drive up to 30 clock lines
*1X and 1/2X configurable outputs
*Output three-state control
*350 ps maximum output-to-output skew
*Pin compatible with MPC949, MPC9449
*Available in Commercial and Industrial temperature range
*52-pin TQFP package

CY29949AXI, CY29949AXIT, CY29949AXC, CY29949AXCT

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General Description
CY25562 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic interference (EMI) found in today’s high speed digital electronic systems.
CY25562 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance.
CY25562 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 1 for programming details.
CY25562 is intended for applications with a reference frequency in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing.
CY25562 is available in an eight-pin SOIC package with a 0 to 70°C operating temperature range.
Refer to CY25561 for applications with lower drive requirements, and CY25560 with lower drive and frequency requirements.

Features
*50 to 200 MHz Operating Frequency Range
*Wide range of spread selections: 9
*Accepts Clock and Crystal Inputs
*Low Power Dissipation
-70 mW Typ (Fin = 65 MHz)
*Frequency Spread Disable Function
*Center Spread Modulation
*Low Cycle-to-cycle Jitter
*8-pin SOIC Package

Applications
*High resolution VGA controllers
*LCD panels and monitors
*Workstations and servers

CY25562SXC, CY25562SXCT

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General Description
CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today’s high speed digital electronic systems.
CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced.
This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance.
CY25561 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 2 for programming details.
CY25561 is intended for use with applications with a reference frequency in the range of 50 to 166 MHz.
A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing.
CY25561 is available in an eight-pin SOIC package with a 0°C to 70°C operating temperature range.

Features
*50 to 166 MHz Operating Frequency Range
*Wide Range of Spread Selections:9
*Accepts Clock and Crystal Inputs
*Low Power Dissipation
-70 mW–Typ at 66 MHz
*Frequency Spread Disable Function
*Center Spread Modulation
*Low Cycle-to-cycle Jitter
*8-pin SOIC Package

Applications
*Desktop, notebook, and tablet PCs
*VGA controllers
*LCD panels and monitors
*Workstations and servers

CY25561SXC, CY25561SXCT

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Description
The LUPA 1300-2 is a highly integrated SXGA high speed, high sensitivity CMOS image sensor targeted at various high speed machine vision and industrial monitoring applications. The sensor runs at 500fps and features triggered and pipelined shutter modes. The sensor packs 24 parallel 10-bit A/D converters with an aggregate conversion rate of 740 MSPS.
On-chip digital column FPN correction allows the sensor to output ready-to-use image data for all but the most demanding applications. In order to allow simple and reliable system integration, the 13 channel 8 Gbps LVDS serial link protocol supports per channel skew correction and serial link integrity monitoring. Peak responsivity of the 14x14um 6T pixel is 7350
V.m2/W.s. Dynamic range is measured to be 57dB. In full frame video mode, the sensor consumes 1.2W from a 2.5V power supply. The sensors integrates A/D conversion, on-chip timing for a wide range of operating modes and features an LVDS interface for easy system integration. By removing the visually highly disturbing column patterned noise, this sensor allows building a camera without having to perform any off-line correction or the need for any memory making this sensor highly suitable for lower cost applications. Moreover, since the on-chip column FPN correction is more reliable than an off-line correction as it is intrinsically compensated for supply and temperature variations, this sensor also allows to build reliable high-end camera's without having to worry about column FPN appearing in environments with highly varying ambient temperatures.
The sensor requires only one master clock for operation up to 500 fps. It is housed in a 168-pin ceramic μPGA package.
The LUPA 1300-2 is available in a monochrome version or Bayer (RGB) patterned color filter array and is available with and without glass.

Features
*1280 x 1024 active pixels
*14 μm X 14 μm square pixels
*1" optical format
*Monochrome or color digital output
*500 fps frame rate
*On-chip 10-bit ADCs
*12 LVDS serial outputs
*Random programmable ROI readout
*Pipelined, Triggered and Snapshot shutter
*On-chip column FPN correction
*Serial to Parallel Interface (SPI)
*Limited supplies: Nominal 2.5V (some supplies require 3.3V)
*0°C to 70°C operational temperature range
*168-pin uPGA package
*Power dissipation: 1.2W

Applications
*High speed machine vision
*Motion analysis
*Intelligent traffic system
*Medical imaging
*Industrial imaging

CYIL2SM1300AA-GDCES, CYIL2SM1300AA-GWCES, CYIL2SC1300AA-GDCES, CYIL2SC1300AA-GWCES
TAG CMOS, Sensor

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Introduction
The enCoRe II LV family brings the features and benefits of the enCoRe II to non USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip.
The enCoRe II LV is a low voltage, low cost 8-bit Flash programmable microcontroller.
The enCoRe II LV features up to 36 GPIO pins. The IO pins are grouped into five ports (Port 0 to 4). The pins on Ports 0 and 1 are configured individually, when the pins on Ports 2, 3, and 4
are only configured as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output with up to five pins that
support programmable drive strength of up to 50 mA sink current. Additionally, each IO pin is used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2–P0.4).
The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal is used to provide a higher precision reference. The enCoRe II LV also supports external clock.
The enCoRe II LV has 8 Kbytes of Flash for user code and 256 bytes of RAM for stack space and user variables.
In addition, enCoRe II LV includes a watchdog timer, a vectored interrupt controller, a 16-bit free running timer with capture registers, and a 12-bit programmable interval timer. The power
on reset circuit detects when power is applied to the device, resets the logic to a known state, and executes instructions at Flash address 0x0000. When power falls below a programmable
trip voltage, it generates a reset or is configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. This is configurable to generate a LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The watchdog timer ensures the firmware never gets stalled in an infinite loop.
The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR or POR, a programmable interval
timer, a nominal 1.024 ms programmable output from the free running timer, two capture timers, five GPIO ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, and an internal
wakeup timer interrupt. The wakeup timer causes periodic interrupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge-sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling.
The free running timer generates an interrupt at 1024 μs rate. It also generates an interrupt when the free running counter overflow occurs—every 16.384 ms. The duration of an event
under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers
save a programmable 8-bit range of the free running timer when a GPIO edge occurs on the two capture pins (P0.5 and P0.6). The two 8-bit capture registers are ganged into a single 16-bit
capture register.
The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface.

Features
*enCoRe™ II Low Voltage (enCoRe II LV)—enhanced component reduction
- Internal crystalless oscillator with support for optional external clock or external crystal or resonator
- Configurable IO for real world interface without external components
*Enhanced 8-bit microcontroller
- Harvard architecture
- M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal
*Internal memory
- 256 bytes of RAM
- 8 Kbytes of Flash including EEROM emulation
*Low power consumption
- Typically 2.25 mA at 3 MHz
- 5 μA sleep
*In-system reprogrammability
- Allows easy firmware update
*General purpose IO ports
- Up to 36 General Purpose IO (GPIO) pins
- 2 mA source current on all GPIO pins. Configurable 8 or 50 mA per pin current sink on designated pins
- Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output
- Maskable interrupts on all IO pins
*SPI serial communication
- Master or slave operation
- Configurable up to 2 Mbit per second transfers
- Supports half duplex single data line mode for optical sensors
*2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times
- Two registers each for two input pins
- Separate registers for rising and falling edge capture
- Simplifies interface to RF inputs for wireless applications
*Internal low power wakeup timer during suspend mode
- Periodic wakeup with no external components
*Programmable interval timer interrupts
*Reduced RF emissions at 27 MHz and 96 MHz
*Watchdog timer (WDT)
*Low voltage detection with user selectable threshold voltages
*Improved output drivers to reduce EMI
*Operating voltage from 2.7V to 3.6V DC
*Operating temperature from 0–70°C
*Available in 24 and 40-pin PDIP, 24-pin SOIC, 24-pin QSOP and SSOP, 28-pin SSOP, and 48-pin SSOP
*Advanced development tools based on Cypress PSoC® tools
*Industry standard programmer support

Applications
The CY7C601xx and CY7C602xx are targeted for the following applications:
*PC wireless HID devices
- Mice (optomechanical, optical, trackball)
- Keyboards
- Presenter tools
*Gaming
- Joysticks
- Gamepad
*General purpose wireless applications
- Remote controls
- Barcode scanners
- POS terminal
- Consumer electronics
- Toys

CY7C602xx, CY7C60123-PVXC, CY7C60123-PXC, CY7C60113-PVXC,
CY7C60223-PXC, CY7C60223-SXC, CY7C60223-QXC

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Features
*SLIM™ Architecture, allowing simultaneous and independent data paths between Processor & USB and between USB & Mass Storage
*High-Speed USB at 480 Mbps
- USB 2.0 compliant
- Integrated USB 2.0 transceiver, smart Serial Interface Engine
- 16 programmable endpoints
*Mass Storage device support
- MMC/MMC+/SD
- NAND flash: x8 or x16, SLC
- Full NAND management (ECC, wear-leveling)
*Memory-mapped interface to main processor
*DMA slave support
*Ultra low-power, 1.8V core operation
*Low Power Modes
*Small footprint, 6x6mm VFBGA
*Selectable Clock Input Frequencies
- 19.2 MHz, 24 MHz, 26 MHz, 48 MHz

Applications
*Cellular Phones
*Portable Media Players
*Personal Digital Assistants
*Digital Cameras
*Portable Video Recorder

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Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks.

Features
*Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
*1:10 differential outputs
*External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input
*SSCG: Spread Aware™ for EMI reduction
*48-pin SSOP and TSSOP packages
*Conforms to JEDEC JC40 and JC42.5 DDR specifications

CY2SSTV850OC, CY2SSTV850OCT, CY2SSTV850ZC, CY2SSTV850ZCT

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Features
* Compliant with Intel® CK-Titan Clock Synthesizer/Driver Specifications
* Multiple output clocks at different frequencies
* Three pairs of differential CPU outputs, up to 200 MHz
* Ten synchronous PCI clocks, three free-running
* Six 3V66 clocks
* Two 48-MHz clocks
* One reference clock at 14.318 MHz
* One VCH clock
* Spread Spectrum clocking (down spread)
* Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)
* Three Select inputs (Mode select & IC Frequency Select)
* OE and Test Mode support
* 56-pin SSOP package and 56-pin TSSOP package

Benefits
* Supports next-generation Pentium® processors using differential clock drivers
* Motherboard clock generator
* Support Multiple CPUs and a chipset
* Support for PCI slots and chipset
* Supports AGP, DRCG reference and Hub Link
* Supports USB host controller and graphic controller
* Supports ISA slots and I/O chip
* Enables reduction of electromagnetic interference (EMI) and overall system cost
* Enables ACPI-compliant designs
* Supports up to four CPU clock frequencies
* Enables ATE and “bed of nails” testing
* Widely available, standard package enables lower cost

W320-03H
W320-03HT
W320-03X
W320-03XT

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