Description
The ATR0603 is a single-IF GPS front-end IC, designed to meet the requirements of mobile and automotive applications. Excellent RF performance combined with high bandwidth and a low noise figure enables high-quality GPS solutions, and its very low power consumption is a perfect match for portable devices. Featuring a fully integrated balanced frequency synthesizer, only a few external components are required. The gain of the IF amplifier can be set to three different levels in order to meet the requirements for various applications. Several types of external oscillators can be connected to the robust TCXO interface. The startup logic allows significant power saving due to very low power-down current and the ability to disable the external TCXO or even other external components. CMOS output drivers deliver a 1-bit data signal and a 16.367667-MHz clock signal to the baseband interface.

Features
*Very Low Power Design
*Single IF Architecture
*Excellent Noise Performance
*1-bit ADC on Chip
*Small QFN Package (4 mm × 4 mm, 24 Pins)
*Highly Integrated, Few External Components
*Advanced BiCMOS Technology (UHF6s)
*Supply Switch for External Circuitry (e.g., TCXO)
*Non-ESD-sensitive Device

ATR0603-PFQW
TAG Front-end, GPS, ic

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Description
The ATR2732N1 is a front-end monolithic integrated circuit, manufactured using Atmel®’s silicon-germanium BiCMOS process (SiGMOS).
The ATR2732N1 carries out all functions of RF and IF processing, as well as the clock-signal generation for these functions. Therefore, there is an integrated fractional PLL, which, equivalent to most of the other functions, can be controlled via an external digital bus. The RF functions include LNA, down-conversion mixing, amplifying, detection, and gain control. An external SAW filter is required in the signal path after the RF functions. Additional amplifiers with detection and control functions are integrated IF functions.
The device offers several tuning support functions, and was created to simplify the design and manufacturing process. To this end, the number of external components are minimal.
The part fits perfectly to Atmel’s DAB baseband processor ATR2740.

Features
*ATR2732N1 is a Special Version of ATR2732 Recommended for Automotive Applications
*Highly Integrated DAB Front-end Solution Covering Band III and L-band Reception
*Convenient Internal Clock Generation, Single Reference Clock
*Fractional PLL for VHF
*Fully Integrated VCOs
*High-precision Digitally Tunable Reference Oscillator
*Integrated High-performance LNAs
*Very Flexible Programming of the AGC
*Automatically Aligned External Filter Tuning
*Simple Three-wire Digital Control Interface for Easy Handling
*Single Low Voltage (3.3V) Supply Operation
*Low Current Consumption Due to Several Power-down Options
*Small SMD Package (QFN 9 mm × 9 mm)

Applications
*Commercial DAB Receivers
*DAB Receiver Solutions for Car Radio Applications
*Portable DAB Solutions

ATR2732N1-PBQW, ATR2732N1-PBPW

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Description
ATA6612/ATA6613 is a System-in-Package (SiP) product, which is particularly suited for complete LIN-bus slave-node applications. It supports highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel®’s series of AVR 8-bit microcontroller with advanced RISC architecture.
The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with 16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts.
In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5 the LIN SBC is described, and in sections 6 to 7 the AVR is described in detail.

General Features
*Single-package Fully-integrated AVR® 8-bit Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
*Very Low Current Consumption in Sleep Mode
*8 Kbytes/16 Kbytes Flash Memory for Application Program (ATA6612/ATA6613)
*Supply Voltage Up to 40V
*Operating Voltage: 5V to 27V
*Temperature Range: Tcase –40°C to +125°C
*QFN48, 7 mm × 7 mm Package

ATA6613, ATA6612P-PLQW, ATA6612P-PLPW, ATA6613P-PLQW, ATA6613P-PLPW

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Description
The ATR2732N3 is a front-end monolithic integrated circuit, manufactured using Atmel®’s silicon-germanium BiCMOS process (SiGMOS).
The ATR2732N3 carries out all functions of RF and IF processing, as well as the clock-signal generation for these functions. Therefore, there is an integrated fractional PLL, which, equivalent to most of the other functions, can be controlled via an external digital bus. The RF functions include LNA, down-conversion mixing, amplifying, detection, and gain control. An external SAW filter is required in the signal path after the RF functions. Additional amplifiers with detection and control functions are integrated IF functions.
The device offers several tuning support functions, and was created to simplify the design and manufacturing process. To this end, the number of external components are minimal.
The part fits perfectly to Atmel’s DAB baseband processor ATR2740.

Features
*Highly Integrated DAB Front-end Solution Covering Band III and L-band Reception
*Convenient Internal Clock Generation, Single Reference Clock
*Fractional PLL for VHF
*Fully Integrated VCOs
*High-precision Digitally Tunable Reference Oscillator
*Integrated High-performance LNAs
*Very Flexible Programming of the AGC
*Automatically Aligned External Filter Tuning
*Simple Three-wire Digital Control Interface for Easy Handling
*Single Low Voltage (3.3V) Supply Operation
*Low Current Consumption Due to Several Power-down Options
*Small SMD Package (QFN 9 mm × 9 mm)

Applications
*Commercial DAB Receivers
*DAB Receiver Solutions for Car Radio Applications
*Portable DAB Solutions

ATR2732N3-PBQW, ATR2732N3-PBPW

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Description
Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the use of more advanced and intelligent electronic circuits.
The TSS461E is a circuit which allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thereby, minimizing the electrical wire usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface car body electronics (lights, wipers, power window, etc.).
The TSS461E is fully compliant with the ISO standard 11519-3. This standard supports a wide range of applications such as low-cost remote control switches, typically used for lamp control; complex, highly-autonomous, distributed systems like engine controls, which require fast and secure data transfers.
The TSS461E is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256-bytes of RAM and the register area is divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor to interface with ease to the TSS461E, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461E analyzes the messages received or transmitted according to 6 different criteria including some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagnosis and selection, allowing for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus.

Features
*Fully Compliant to VAN Specification ISO/11519.3
*Handles All Specified Module Types
*Handles All Specified Message Types
*Handles Retransmission of Frames on Contention and Errors
*3 Separate Line Inputs with Automatic Diagnosis and Selection
*1 Mbit/s Maximum Transfer Rate
*Normal or Pulsed (Optical and Radio Mode) Coding
*Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor Interface
*Multiplexed Address and Data Bus
*Idle and Sleep Modes
*128 Bytes of General-purpose RAM
*DMA Capabilities for Message Handling
*14 Identifier Registers with All Bits Individually Maskable
*6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the Reset Pin
*Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output
*Single +5V Power Supply
*0.5 mm CMOS Technology
*SOP 24 Packaging

TSS461E-TDSA-9, TSS461E-TDRA-9, TSS461E-TDRZ-9

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Description and Applications
The TSS901E provides an interface between a Data-Strobe link - according to the IEEE Std 1355-1995 specification carrying a simple interprocessor communication protocol - and a data processing node consisting of a CPU and a communication and data memory.
The TSS901E offers hardware supported execution of the major parts of the interprocessor communication protocol: data transfer between two nodes of a multi-processor system is performed with minimal host CPU intervention. The TSS901E can execute simple commands to provide basic features for system control functions; a provision of fault tolerant features exists as well.
Although the TSS901E initial exploitation is for use in multi-processor systems where the high speed links standardisation is an important issue and where reliability is a requirement, it could be used in applications such as heterogeneous systems or modules without any communication feature like special image compression chips, some signal processors, application specific programmable logic or mass memory.
The TSS901E may also be used in single board systems where standardised high speed interfaces are needed and systems containing "non-intelligent" modules such as A/D-converter or sensor interfaces which can be assembled with the TSS901E thanks to the "control by link" feature.

Features
*3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1.25 up to 200 Mbit/s in each direction
*A COmmunication Memory Interface (COMI) provides autonomous accesses to a communication memory which are controlled by an arbitration unit, allowing two TSS901E to share one Dual Port Ram without external arbitration
*The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type
*Little or big endian mode is configurable
*AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E configuration registers and to the DS-link channels for the controlling CPU
*Device control via one of the three links allows its use in systems without a local controller
*Link disconnect detection and parity check at token (data and control) level; possible checksum generation for packet level check
*Power saving mode relying on automatic transmit rate reduction
*A user’s manual of the TSS901E (also called SMCS332) is available at:
http://www.spacewire.esa.int/tech/spacewire/products/index.htm
*Designed on Atmel MG1140E matrix and packaged into MQFPL196

TSS901EMA-E

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Description
The T89C51AC2 is a high performance CMOS FLASH version of the 80C51 CMOS single chip 8-bit microcontrollers. It contains a 32Kbytes Flash memory block for program and data.
The 16K bytes or 32K bytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.
The T89C51AC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51AC2 has a 10 bits A/D converter, a 2Kbytes Boot Flash Memory, 2 Kbytes EEPROM for data, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART).
The fully static design of the T89C51AC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
The T89C51AC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.
The added features of the T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, ...
While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Features
*80C51 core architecture:
*256 bytes of on-chip RAM
*1Kbytes of on-chip XRAM
*32 Kbytes of on-chip Flash memory
*2 Kbytes of on-chip Flash for Bootloader
*2 Kbytes of on-chip EEPROM
*14-source 4-level interrupt
*Three 16-bit timer/counter
*Full duplex UART compatible 80C51
*maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)
*Five ports: 32 + 2 digital I/O lines
*Five channel 16-bit PCA with:
- PWM (8-bit)
- High-speed output
- Timer and edge capture
*Double Data Pointer
*21 bit watchdog timer (including 7 programmable bits)
*A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs
*20 microsecond conversion time
*Two conversion modes
*On-chip emulation Logic (enhanced Hook system)
*Power saving modes:
*Idle mode
*Power down mode
*Power supply: 5V +/- 10% (or 3V** +/- 10%)
*Temperature range: Industrial (-40 to +85C)
*Packages: TQFP44, PLCC44

T89C51AC2-RLSC-M, T89C51AC2-SLSC-M, T89C51AC2-RLTC-M
TAG A/D, EEPROM, Flash, MCU

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Description
The AT24C128B provides 131,072 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V)
version.

Features
*Low-voltage and Standard-voltage Operation
*1.8 (VCC = 1.8V to 5.5V)
*Internally Organized as 16,384 x 8
*Two-wire Serial Interface
*Schmitt Trigger, Filtered Inputs for Noise Suppression
*Bidirectional Data Transfer Protocol
*1 MHz (5.5V, 2.5V), and 400 kHz (1.8V) Compatibility
*Write Protect Pin for Hardware and Software Data Protection
*64-byte Page Write Mode (Partial Page Writes Allowed)
*Self-timed Write Cycle (5 ms Max)
*High Reliability
*Endurance: One Million Write Cycles
*Data Retention: 40 Years
*Lead-free/Halogen-free
*8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 Packages
*Die Sales: Wafer Form, Tape and Reel and Bumped Wafers

AT24C128B-PU, AT24C128BN-SH-B, AT24C128BN-SH-T, AT24C128B-TH-B, AT24C128B-TH-T, AT24C128BY6-YH-T, AT24C128BD3-DH-T, AT24C128BU2-UU-T, AT24C128B-W-11
TAG EEPROM, Serial

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Description
The AT29LV1024 is a 3-volt only in-system Flash programmable and erasable rea donly memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 50 mA. The device endurance issuch that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV1024 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading f rom an EPROM. Reprogramming the AT29LV1024 is performed on a sector basis; 128 words of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7 or I/O15. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Features
*Single Voltage, Range 3V to 3.6V Supply
*3-Volt Only Read and Write Operation
*Software Protected Programming
*Fast Read Access Time - 150 ns
*Low Power Dissipation
– 15 mA Active Current
– 50 μA CMOS Standby Current
*Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (128 words/sector)
– Internal Address and Data Latches for 128 Words
*Fast Sector Program Cycle Time - 20 ms
*Internal Program Control and Timer
*DATA Polling for End of Program Detection
*Typical Endurance > 10,000 Cycles
*CMOS and TTL Compatible Inputs and Outputs
*Commercial and Industrial Temperature Ranges

AT29LV1024-15JC, AT29LV1024-15TC, AT29LV1024-15JI, AT29LV1024-15TI, AT29LV1024-20JC, AT29LV1024-20TC, AT29LV1024-20JI, AT29LV1024-20TI, AT29LV1024-25JC, AT29LV1024-25TC, AT29LV1024-25JI, AT29LV1024-25TI
TAG Memory

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Description
The AT93C46/56/57/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64/128/256 words of 16
bits each, when the ORG Pin is connected to VCC and 128/256/512 words of 8 bits
each when it is tied to ground.
The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential.
The AT93C46/56/57/66 is available in space saving 8-pin PDIP and 8-pin JEDEC and
EIAJ SOIC packages.

Features
*Low Voltage and Standard Voltage Operation
-5.0 (VCC = 4.5V to 5.5V)
-2.7 (VCC = 2.7V to 5.5V)
-2.5 (VCC = 2.5V to 5.5V)
-1.8 (VCC = 1.8V to 5.5V)
*User Selectable Internal Organization
-1K: 128 x 8 or 64 x 16
-2K: 256 x 8 or 128 x 16
-4K: 512 x 8 or 256 x 16
*3-Wire Serial Interface
*2 MHz Clock Rate (5V) Compatibility
*Self-Timed Write Cycle (10 ms max)
*High Reliability
-Endurance: 1 Million Write Cycles
-Data Retention: 100 Years
-ESD Protection: >4000V
*Automotive Grade and Extended Temperature Devices Available
*8-Pin PDIP, 8-Pin JEDEC and EIAJ SOIC, and 8-Pin TSSOP Packages

AT93C46-10PC
AT93C46-10SC
AT93C46R-10SC
TAG EEPROM

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