DESCRIPTION
The AZ10/100LVEL16 is a differential receiver. The device is functionally equivalent to the E116 device with higher performance capabilities. With output transition times significantly faster than the E116, the LVEL16 is ideally suited for interfacing with high frequency sources.
The LVEL16 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the D/D¯ differential input pair. The input signal is then fed to the other D/D¯ input. The VBB pin can support 1.5 mA sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01 μF capacitor.
Under open input conditions internal input clamps will force the Q output LOW.

FEATURES
*Green and RoHS Compliant / Lead (Pb) Free Packages available
*250ps Propagation Delay
*High Bandwidth Output Transitions
*Operating Range of 3.0V to 5.5V
*Internal Input Pulldown Resistors
*Direct Replacement For ON Semiconductor MC10EL16, MC100EL16, & MC100LVEL16
*IBIS Model Files Available on Arizona Microtek Website

AZ10LVEL16D, AZ100LVEL16D, AZ10LVEL16T, AZ100LVEL16T, AZ100LVEL16NG

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DESCRIPTION
The AZ10/100EP16VS is a Silicon–Germanium (SiGe) differential receiver with variable output swing. The EP16VS has functionality and output transition times similar to the EP16, with an input that controls the amplitude of the Q/Q¯ outputs.
Connecting the BOOST pin to VEE increases the output swing by about 15% above standard ECL/PECL levels. The BOOST pin is internally tied to VEE for the SOIC 8 and TSSOP 8 packages, and is under external user control for the MLP 16 package. When both the BOOST pin and the VCTRL pin are not connected, the part operates with the standard ECL/PECL output and VBB levels of the AZ10/100EP16 device. To ensure best performance, the BOOST
pin should be tied to VEE when the variable swing feature is used.
The operational range of the EP16VS control input, VCTRL, is from VREF (full swing) to VCC (min. swing). Maximum swing is achieved by leaving the VCTRL pin open or tied to VEE. Simple control of the output swing can be obtained by a variable resistor between the VREF and VCC pins, with the wiper driving VCTRL. Typical application circuits and results are described in this Data Sheet.
The EP16VS provides a VREF (VBB/VREF) output for a DC bias when AC coupling to the device. The VREF pin should be used only as a bias for the EP16VS as its current sink/source capability is limited. Whenever used, the VREF pin should be bypassed to ground via a 0.01μF capacitor.
Under open input conditions for D/D¯, the Q/Q¯ outputs are not guaranteed.

FEATURES
*Silicon-Germanium for High Speed Operation
*150ps Typical Propagation Delay
*AZ100EP16VS Functionally Equivalent to ON Semiconductor MC100EP16VS at 3.3V
*Available in a 3x3mm MLP Package
*S-Parameter (.s2p) and IBIS Model Files available on Arizona Microtek Website

AZ100EP16VS, AZ10EP16VSD, AZ100EP16VSD, AZ10EP16VST, AZ100EP16VST

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DESCRIPTION
The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the ELT23 makes it ideal for applications that require the translation of a clock and a data signal.
The ELT23 is available in only the ECL 100K standard. Since there are no PECL outputs or an external VBB reference, the ELT23 does not require both ECL standard versions. The PECL inputs are differential; there is no specified difference between the differential input 10K and 100K standards. Therefore the AZ100ELT23 can accept any standard differential PECL input referenced from a VCC of 3.0V to 5.5V.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*Green / RoHS Compliant / Lead (Pb) Free package available
*3.5ns Typical Propagation Delay
*<500ps Typical Output to Output Skew
*Differential PECL Inputs
*CMOS/TTL Outputs
*Flow Through Pinouts
*Direct Replacement for ON Semiconductor MC100ELT23
*Operating Range of 3.0V to 5.5V (For operation down to 2.5V consult AZM)
*Use AZ100ELT23 for 10K Applications

AZ100ELT23D, AZ100ELT23D+, AZ100ELT23DG, AZ100ELT23T, AZ100ELT23T+
TAG CMOS, TTL

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DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pulldown resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of ≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details.
When the AZP94 is disabled, the Q and Q¯ outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled.

FEATURES
• Green and RoHS Compliant / Lead (Pb) Free Package Available
• 3.0V to 5.5V Operation
• Selectable Divide Ratio
• Selectable Enable Polarity and Threshold (CMOS/TTL or PECL)
• Tristate Compatible Outputs
• Input Buffer Powers Down when Disabled
• Selectable Input Biasing
• High Bandwidth for ≥1GHz
• Available in a MLP 8 (2x2) Package
• IBIS Model File Available on Arizona Microtek Website

AZP94NAG, AZP94XP

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DESCRIPTION
The AZ10/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those applications that require the ultimate in AC performance.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*230ps Propagation Delay
*High Bandwidth Output Transitions
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semiconductor MC10EL01 & MC100EL01

AZ100EL01

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DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*700 MHz Minimum Shift Frequency
*9-Bit for Byte-Parity Application
*Asynchronous Master Reset
*Dual Clocks
*Operating Range of 4.2V to 5.46V
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semi MC10E142 & MC100E142

AZ100E142, AZ10E142FN, AZ100E142FN

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DESCRIPTION
The AZ10/100LVEL11 is a differential 1:2 fanout gate.
The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open input conditions.
If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*265ps Propagation Delay
*5ps Skew Between Outputs
*High Bandwidth Output Transitions
*Internal Input Pulldown Resistors
*Operating Range of 3.0V to 5.5V
*Direct Replacement for ON Semi
-MC100LVEL11, MC10EL11
-& MC100EL11
*Transistor Count = 51

AZ100LVEL11

TAG Buffer

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DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs.
Each flip-flop may be locked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops.
In this case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn).
Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
* 1100 MHz Min. Toggle Frequency
* Differential Outputs
* Individual and Common Clocks
* Individual Resets (asynchronous)
* Paired Sets (asynchronous)
* Operating Range of 4.2V to 5.46V
* 75kΩ Internal Input Pulldown Resistors
* Direct Replacement for On Semiconductor MC10E131 & MC100E131

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DESCRIPTION
The AZ10/100ELT22 is a dual CMOS/TTL to differential PECL translator.
Because PECL (Positive ECL) levels are used, only VCC and ground are required.
The small outline packaging and the low skew, dual gate design of the ELT22 makes it ideal for applications that require the translation of a clock and a data signal.
The ELT22 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while the 100ELT is compatible with PECL 100K logic levels.
NOTE: Specifications in PECL tables are valid when thermal equilibrium is established.

FEATURES
* Green / RoHS Compliant / Lead (Pb) Free package available
* 0.5ns Typical Propagation Delay
* <100ps Typical Output to Output Skew
* Differential PECL Outputs
* Flow Through Pinouts
* Operating Range of 3.0V to 5.5V
* Direct Replacement for ON Semiconductor MC10ELT22, MC100ELT22, MC100LVELT22 & Micrel SY89322V
* IBIS Model Files Available on Arizona Microtek Website

AZ100ELT22
AZ10ELT22D
AZ100ELT22D
AZ100ELT22DG
AZ100ELT22T
AZ100ELT22TG

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DESCRIPTION
 The AZ10/100ELT20 is a CMOS/TTL to differential PECL translator.
It operates with a single power supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications.
The extremely small MLP 8 2x2 mm package makes it ideal for those applications where space, performance and low power are at a premium.
When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW. The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels while the AZ100ELT20 is compatible with PECL 100K logic levels.

FEATURES
* 0.5ns Typical Propagation Delay
* Differential PECL Outputs
* Flow Through Pinouts
* Operating Range of +3.0V to +5.5V
* Direct Replacement for ON Semi MC10ELT20, MC100ELT20, MC100LVELT20 & Micrel SY89329V
* Available in 2x2 and 3x3 mm MLP Packages
* IBIS Model Files Available on Arizona Microtek Website

AZ100ELT20
AZ100ELT20D
AZ100ELT20DG
AZ100ELT20TG
AZ10/100ELT20XP

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