GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to incoming digital signals to receive the data stream. The transmitter and receiver each support differential PECL-compatible I/O for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically.
Figure 1 shows a typical network configuration incorporating the chipset. The chipset is compatible with AMCC’s S2036 Open Fiber Control (OFC) device.

FEATURES
*Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
*S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
*S2043 receiver PLL configured for clock and data recovery
*1062, 531 and 266 Mb/s operation
*10- or 20-bit parallel TTL compatible interface
*1 watt typical power dissipation for chipset
*+3.3/+5V power supply
*Low-jitter serial PECL compatible interface
*Lock detect
*Local loopback
*10mm x 10mm 52 PQFP package
*Fibre Channel framing performed by receiver
*Continuous downstream clocking from receiver
*TTL compatible outputs possible with +5V I/O power supply

APPLICATIONS
High-speed data communications
*Supercomputer/Mainframe
*Workstation
*Switched networks
*Proprietary extended backplanes
*Mass storage devices/RAID drives

S2043, S2042B-10, S2043B-10

GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI encoding transmitter and CMI decoding receiver. The chip derives high speed timing and data signals for SONET/SDH or PDH-based equipment. The circuit is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figures 1a and 1b show typical network applications.
The S3031B has two independent VCOs which are synchronized to the local NRZ transmitted data and the received CMI data respectively. The chip can be used with either a 19.44 MHz or a 38.88 MHz reference clock when operated in the SONET/SDH OC-3 mode. In E4 mode the chip can be operated with a 17.408 MHz or a 34.816 MHz reference in support of existing system clocking schemes. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbps and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs and the PECL nibble clock interface guarantee compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3031B is packaged in a 0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components onchip for a coaxial cable interface, including analog transformer driver circuitry and equalization interface circuitry. Discrete controls permit separate selection of CMI or NRZ operation and analog (coaxial copper) or PECL (optical module) media interfaces. Both line loopback and diagnostic local loopback operation are supported.

FEATURES
*Complies with Bellcore and ITU-T specifications
*On-chip high-frequency PLLs for clock generation and clock recovery
*On-chip analog circuitry for transformer driver and equalization
*Supports 139.264 Mbps (E4) and 155.52 Mbps (OC-3) transmission rates
*Supports 139.264 Mbps and 155.52 Mbps Coded Mark Inversion (CMI) interfaces
*TTL Reference frequencies of 19.44 and 38.88 MHz (OC-3) or 17.408 and 34.816 MHz (E4)
*Interface to both PECL and TTL logic
*Lock detect on clock recovery function — monitors run length and frequency
*Serial and 4 bit (nibble) system interfaces
*Low jitter PECL interface
*+5V operation
*100 PQFP/TEP package
*Supports both electrical and optical interfaces

APPLICATIONS
*ATM over SONET/SDH
*OC-3/STM-1 or E4-based transmission systems
*OC-3/STM-1 or E4 modules
*OC-3/STM-1 or E4 test equipment
*Section repeaters
*Add Drop Multiplexers (ADM)
*Broadband cross-connects
*Fiber optic terminators
*Fiber optic test equipment

S3031BH0

GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW.
The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.

FEATURES
*Operating rate
*1250 MHz (Gigabit Ethernet) line rates
*Half and full VCO output rates
*Functionally compliant IEEE 802.3z Gigabit Ethernet standard
*Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference
*Receiver PLL provides clock and data recovery
*10-bit parallel TTL compatible interface
*Low-jitter serial LVPECL compatible interface
*Local loopback
*Single +3.3 V supply, 620 mW power dissipation
*64 PQFP or TQFP package
*Continuous downstream clocking from receiver
*Drives 30 m of Twinax cable directly

APPLICATIONS
*Workstation
*Frame buffer
*Switched networks
*Data broadcast environments
*Proprietary extended backplanes

S2060A, S2060B, S2060C, S2060D

DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities.
The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applications to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5935 is a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5935 can become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec. The S5935 PCI controller also maintains dropin compatibility for upgrading many existent S5933 designs requiring migration into new motherboard architectures, PCI BIOSs and software operating systems.

FEATURES
*PCI 2.1 Compliant Master/Slave Device
*Full 132 Mbytes/sec Transfer Rate
*Supports new Intel 440BX/GX Chipsets
*Supports new WinNT Service Pack 2 & 3
*PCI Bus Operation DC to 33 MHz
*8/16/32 Bit Add-On User Bus
*Four Definable Pass-Thru Data Channels
*Two 32 Byte Internal FIFOs w/DMA
*Synchronous Add-On Bus Operation
*Mail Box Registers w/Byte Level Status
*Direct Mail Box Data Strobe/Interrupts
*Direct PCI & Add-On Interrupt Pins
*Optional Non-Volatile Memory Boot Loading
*Optional Expansion BIOS/POST Code

APPLICATIONS
*High Speed Networking
*Digital Video Applications
*I/O Communications Ports
*High Speed Data Input/Output
*Multimedia Communications
*Memory Interfaces
*High Speed Data Acquisition
*Data Encryption/Decryption
*Intel i960 Interface
*General Purpose PCI Interfacing
*Existent S5933 Design Upgrades*

S5935QF, S5935QRC, S5935TFC

DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed the S5335 to solve the problem of interfacing applications to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5335 is a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5335 can become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec. The S5335 was designed for 3.3V environment but its inputs/outputs are tolerant to 5V signaling.

FEATURES
*PCI 2.1 Compliant Master/Slave Device
*Full 132 Mbytes/sec Transfer Rate
*PCI Bus Operation DC to 33 MHz
*8/16/32 Bit Add-On User Bus
*3.3V Power Supply
*5V Tolerant I/Os
*Four Definable Pass-Thru Data Channels
*Two 32 Byte Internal FIFOs w/DMA
*Synchronous Add-On Bus Operation
*Mail Box Registers w/Byte Level Status
*Direct Mail Box Data Strobe/Interrupts
*Direct PCI & Add-On Interrupt Pins
*Optional Non-Volatile Memory Boot Loading
*Optional Expansion BIOS/POST Code
*176 Pin LQFP
*Environmental Friendly Lead-Free Package Option

APPLICATIONS
*High Speed Networking
*Digital Video Applications
*I/O Communications Ports
*High Speed Data Input/Output
*Multimedia Communications
*Memory Interfaces
*High Speed Data Acquisition
*Data Encryption/Decryption
*Intel i960 Interface
*General Purpose PCI Interfacing

S5335QF, S5335QFAAB, S5335DK

Description
Designed specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a highperformance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.
This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.

Features
*PowerPC‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking)
*On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory
*Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details)
*Supports up to 4 GB (2 Chip Selects) of 64-bit/32-bit SDRAM with ECC
– DDR1 266-333-400
– DDR2 400-533-667
*Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support for
conventional PCI
*XOR Accelerator with DMA controller
*Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P &
Q parity computations, supports up to 255 drives
*I2O Messaging Unit with two DMA controllers
*External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices
*One Ethernet 10/100/1000 Mbps half- or fullduplex interface. Operational modes supported
are MII and GMII.
*Programmable Interrupt Controller supports interrupts from a variety of sources.
*Programmable General Purpose Timers (GPT)
*Three serial ports (16750 compatible UART)
*Two IIC interfaces
*General Purpose I/O (GPIO) interface available
*JTAG interface for board level testing
*Processor can boot from PCI memory

PPC440SP, PPC440SP-AFC533C, PPC440SP-RFC533C

Description
The S19250 MUX/DeMux chip is a fully integrated serialization/de-serialization SONET STS-192/10 GB Ethernet/Fiber Channel transceiver with Electronic Dispersion Compensation (EDC).
This device can be used to compensate channel impairments caused by Single Mode Fiber (SMF) and copper medium.
The chip performs all necessary parallel-to-serial and serial-to-parallel functions in onformance
with SONET/SDH, 10 Gigabit Ethernet (10 GbE) and 10 Gigabit Fibre Channel (10 G FC) transmission standards.
The figure below shows a typical network application.
The other application block diagrams are shown on page 2.
On-chip clock synthesis PLL components are contained in the S19250 chip, allowing the use
of a slower external transmit clock reference.
The chip can be used with 155.52 MHz or 622.08 MHz (or equivalent FEC/10 GbE/10 G FC rates) reference clocks, in support of existing system clocking schemes.
The low-jitter LVDS interface guarantees compliance with the biterror rate requirements of the Telcordia and ITUT standards.

Features
*Operational from 9.9 Gbps to 11.3 Gbps
*Built-In Self Test (BIST) with Error Counter
*On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.
*16-bit LVDS Parallel Data Path
*TX and RX Lock Detect Indicators
*Reference Loop Timing Modes
*Line and Diagnostic Loopback Mode for Faulty Node Identification
*-40°C to 85°C Industrial Temperature Range
*Supports MDIO, I2C and SPI serial interface
*Complies with applicable OIF SFI-4 Phase 1, Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae
and XFP MSA Standards
*2000 V ESD rating on low speed pins, 1000 V on high speed I/Os
*17 x 17 mm2, 1.0 mm pitch package with Green / RoHS compliant lead free option. Pin Compatible with S19235/S19237.
*1.1 W typical

Applications
*SONET/SDH and 10GbE-Based Transmission Systems & Modules
*Section Repeaters
*Add Drop Multiplexers (ADM)
*Broad-Band Cross-Connects
*Fiber Optic Test Equipment

Description
Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements.
This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-12E, 0.25 μm (0.18 μm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA)
Power (typical): TBDW at 133MHz, 1.5W at 200MHz, 2W at 266MHz

Features
* PowerPC® 405 32-bit RISC processor core operating up to 266MHz
* Synchronous DRAM (SDRAM) interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
* 4KB on-chip memory (OCM)
* External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and external peripherals
- Up to eight devices
- External Mastering supported
* DMA support for external peripherals, internal UART and memory
- Scatter-gather chaining supported
- Four channels
* PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
- Synchronous or asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
* Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII)
* Programmable interrupt controller supports seven external and 19 internal edge triggered or levelsensitive interrupts
* Programmable timers
* Two serial ports (16550 compatible UART)
* One IIC interface
* General purpose I/O (GPIO) available
* Supports JTAG for board level testing
* Internal processor local Bus (PLB) runs at SDRAM interface frequency
* Supports PowerPC processor boot from PCI memory

GENERAL DESCRIPTION
 The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment.
The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock.
The chip outputs a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
The phase detector compares the phase relationship between the VCO output and the serial data input.
A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.
A block diagram is shown in Figure 2.
There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.

FEATURES
* Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
* Five on-chip high frequency PLLs with internal loop filters for clock recovery
* Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
* Clock Multiplier PLL for transmit clock generation
* 19.44 or 51.84 MHz reference frequency
* Lock detect—monitors run length and frequency
* Low-jitter differential interface
* 3.3V supply
* Available in a 64-pin TQFP package
* Compatible with IgT WAC-413 ATM Quad- UNI processor

S3029A